Patents Examined by Aracelis Ruiz
  • Patent number: 10606489
    Abstract: Remote copy operations are performed to copy data from a primary storage controller to a secondary storage controller, wherein input/output (I/O) requests are received at the primary storage controller from a host both via a bus interface and a network interface while the remote copy operations are in progress, and wherein consistency groups are formed during the remote copy operations to copy the data consistently. A relocation is performed of data written via the bus interface for a current consistency group from a cache to a sidefile, and subsequently data written via the bus interface for a next consistency group is stored in the cache.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Ward, Matthew J. Kalos, Joshua J. Crawford, Carol S. Mellgren
  • Patent number: 10606490
    Abstract: A storage control device includes circuitry configured to acquire status information indicating a load status and a response status of each of one or more storage devices from the one or more storage devices which are accessed in response to a request transmitted from a host device, detect a first storage device having a load no more than a first threshold value and a response time no less than a second threshold value from the one or more storage devices on the basis of the acquired status information, and execute redundant copy of the detected first storage device.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: March 31, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Koutarou Nimura, Atsushi Igashira, Yasuhiro Ogasawara, Marie Abe, Hiroshi Imamura
  • Patent number: 10599344
    Abstract: Aspects of the innovations herein are consistent with a storage system for storing variable sized objects. According to certain implementations, the storage system may be a transaction-based system that uses variable sized objects to store data, and/or may be implemented using data stores, such as arrays disks arranged in ranks. In some exemplary implementations, each rank may include multiple stripes, each stripe may be read and written as a convenient unit for maximum performance, and/or a rank manager may be provided to dynamically configure the ranks. In certain implementations, the storage system may include a stripe space table that contains entries describing the amount of space used in each stripe. Further, an object map may provide entries for each object in the storage system describing the location, the length and/or version of the object.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: March 24, 2020
    Assignee: Primos Storage Technology LLC
    Inventor: Robert E. Cousins
  • Patent number: 10599337
    Abstract: The present application provides methods and devices for writing data and acquiring data in a distributed storage system. According to an exemplary method, in a process of writing data, a data file is not overwritten but is instead updated by making a copy in a newly allocated storage block and an updated description file is persisted by using an atomic operation. This way, in a process of appending data, it can be ensured that a data file is not damaged, and the readability and consistency of data are maintained, facilitating the use by a user. Further, writing data according to some embodiments of the present application supports a write in which a user specifies a write position of to-be-written data, and also supports a write in which the user does not specify a write position of to-be-written data, thereby improving the flexibility of writing data.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: March 24, 2020
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventors: Ming Yang, Wenzhao Li, Zhongyu Zou
  • Patent number: 10599564
    Abstract: Embodiments of the application provide a resource reclamation method and a resource reclamation apparatus. The method includes: determining a memory region corresponding to a target tenant included by a heap memory as a target region; and performing resource reclamation on the target region to release the target region.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: March 24, 2020
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventors: Yumin Qi, Sanhong Li, Chuansheng Lu, Jianho Mo, Tongbao Zhang
  • Patent number: 10592120
    Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: March 17, 2020
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely Tsern
  • Patent number: 10592145
    Abstract: An information management system is provided herein that uses machine learning (ML) to predict what data to store in a secondary storage device and/or when to perform the storage. For example, a client computing device can be initially configured to store data in a secondary storage device according to one or more storage policies. A media agent in the information management system can monitor data usage on the client computing device, using the data usage data to train a data storage ML model. The data storage ML model may be trained such that the model predicts what data to store in a secondary storage device and/or when to perform the storage. The client computing device can then be configured to use the trained data storage ML model in place of the storage polic(ies) to determine which data to store in a secondary storage device and/or when to perform the storage.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: March 17, 2020
    Assignee: Commvault Systems, Inc.
    Inventors: Pavan Kumar Reddy Bedadala, Praveen Veeramachaneni
  • Patent number: 10572151
    Abstract: An information handling system includes a dynamic random access memory, and a processor. The dynamic random access memory includes a lower memory portion and multi-channel dynamic random access memory portion. The dynamic random access memory is allocated to operations of a boot process of the information handling system. The processor communicates with the dynamic random access memory. The processor determines whether a fast memory allocation service is detected in the boot process. In response to the fast memory allocation being detected, the processor allocates the multi-channel dynamic random access memory portion of the dynamic random access memory to operations of the boot process.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: February 25, 2020
    Assignee: Dell Products, LP
    Inventors: Swamy Kadaba Chaluvaiah, David K. Chalfant
  • Patent number: 10572160
    Abstract: Technologies are provided for dynamically changing a size of a cache region of a storage device. A storage device controller writes data to the cache region of the storage device using a particular storage format. The storage device controller then migrates the cached data to a storage region of the device, where the data is written using a different storage format. A dynamic cache manager monitors input and output activity for the storage device and dynamically adjusts a size of the cache region to adapt to changes in the input and/or output activity. The dynamic cache manager can also adjust a size of the storage region. The storage device controller can automatically detect that the storage device has dynamic cache support and configure the storage device by creating the cache region and the storage region on the device.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: February 25, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Munif M. Farhan, Phyllis Ng, Darin Lee Frink, Nafea Bshara
  • Patent number: 10564862
    Abstract: A wear leveling method for a rewritable non-volatile memory module, a memory control circuit unit, and a memory storage apparatus are provided. The rewritable non-volatile memory module includes a plurality of physical erasing units. The method includes: recording an operation value of each of the physical erasing units; recording a usage situation value of each of the physical erasing units; and selecting a first physical erasing unit and a second physical erasing unit from the physical erasing units according to the operation values of the physical erasing units and the usage situation values of the physical erasing units and copying valid data stored in the first physical erasing unit to the second physical erasing unit.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: February 18, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 10564878
    Abstract: Implementations of the subject matter described herein provide a storage management method and system. The storage management method comprises: in response to receiving a write request, dividing data to be written into a plurality of data blocks with a predetermined size, the plurality of data blocks having their respective logic block addresses; evenly mapping, based on the logic block addresses, the plurality of data blocks to a plurality of RAID extents of a Redundant Array of Independent Disks (RAID); mapping the plurality of data blocks in the plurality of RAID extents to the disk, so that the plurality of data blocks are distributed in order of size of logic block addresses in the disk.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: February 18, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Jamin Jianbin Kang, Liam Xiongcheng Li, Jian Gao, Geng Han, Xinlei Xu
  • Patent number: 10565103
    Abstract: A method for creating a multi-namespace includes steps of: returning information of a namespace data structure according to a query command from, wherein the information of the namespace data structure comprises a maximum number and a total capacity of supportable namespace; receiving and determining whether a create command for creating a plurality of namespaces is correct, wherein the create command comprises a number of a namespace and a capacity of the namespace; and if the determination is correct, creating a global host logical-flash physical address (H2F) mapping table according to the create command, wherein a number of the global H2F mapping tables is independent of the maximum number of the supportable namespaces and the number of namespace. A method for accessing data in a multi-namespace is also provided.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: February 18, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Po-Sheng Chou
  • Patent number: 10564875
    Abstract: An optical decoding system is applied to mode conversion of a memory. The optical decoding system includes an optical sensor and a processor. The optical sensor is utilized to sense an intensity of a pattern, and variation of the intensity containing an activation code. The processor is electrically connected with the optical sensor. The processor is adapted to analyze the variation of the intensity and to switch the memory from a normal mode to a configuration mode in accordance with the activation code. Normal operation of the memory is paused while the memory is set in the configuration mode.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: February 18, 2020
    Assignee: PixArt Imaging Inc.
    Inventor: Jr-Yi Li
  • Patent number: 10565115
    Abstract: The present disclosure generally relates to prefetching data from one or more CPUs prior to the data being requested by a host device. The prefetched data is prefetched from memory and stored in cache. If a host device requests data that is not already in cache, then a determination is made regarding whether the data is scheduled to be written into cache. If the data is not in cache and is not scheduled to be written into cache, then the data is retrieved from memory and delivered to the host device. If the data is scheduled to be written into cache, or is currently being written into cache, then the request to retrieve the data is delayed or scheduled to retrieve the data once the data is in cache. If the data is already in cache, the data is delivered to the host device.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: February 18, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Kevin James Wendzel
  • Patent number: 10552088
    Abstract: A computer system including: a first computer including a first processor and a first nonvolatile memory; and a second computer including a second processor and a second nonvolatile memory in which the second computer is connected to the first computer. The first computer includes a redundant hardware that, on receiving a write command from the first processor, writes the write data of the write command both into the first nonvolatile memory and into the second computer.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: February 4, 2020
    Assignee: HITACHI, LTD.
    Inventor: Masanori Takada
  • Patent number: 10541009
    Abstract: Devices, systems, and methods having increased efficiency selective writing to memory are disclosed and described. A memory controller, upon receiving a dirty data segment, performs a read-modify-write to retrieve a corresponding data line from memory, saves a copy of the data line, merges the dirty data segment into the appropriate location in the data line to create a modified data line, and generates a write mask from the modified data line and the copy of the data line.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: January 21, 2020
    Assignee: Intel Corporation
    Inventors: David J. Zimmerman, Robert M. Ellis, Rajesh Sundaram
  • Patent number: 10534720
    Abstract: Memory management in a computer system may include allocating memory pages from a physical memory of the computer system to applications executing on the computer system. The memory pages may be associated with memory management tags. One or more memory pages may be identified for processing from the physical memory based on the memory management tags that the memory pages are associated with. The processed memory pages may then be designated as un-allocated memory pages for subsequent allocation to applications executing on the computing system.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: January 14, 2020
    Assignee: VMware, Inc.
    Inventors: Chiao-Chuan Shih, Samdeep Nayak
  • Patent number: 10529396
    Abstract: A system and method to transfer an ordered partial store of data from a controller to a memory subsystem receives the ordered partial store of data into a buffer of the controller. The method also includes issuing a preinstall command to the memory subsystem, wherein the preinstall command indicates that data from a number of addresses of memory corresponding with a target memory location be obtained in local memory of the memory subsystem along with ownership of the data for subsequent use. A query command is issued to the memory subsystem. The query command requests an indication from the memory subsystem that the memory subsystem is ready to receive and correctly serialize the ordered partial store of data. The ordered partial store of data is transferred from the controller to the memory subsystem.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekaterina M. Ambroladze, Sascha Junghans, Matthias Klein, Pak-Kin Mak, Robert J. Sonnelitter, III, Chad G. Wilson
  • Patent number: 10528483
    Abstract: A system includes one or more processor cores and a cache hierarchy. The cache hierarchy includes a first-level cache, a second-level cache, and a third-level cache. The cache hierarchy further includes cache hierarchy control logic configured to implement a caching policy in which each cacheline cached in the first-level cache has a copy of the cacheline cached in at least one of the second-level cache and the third-level cache. The caching policy further provides that an eviction of a cacheline from the second-level cache does not trigger an eviction of a copy of that cacheline from the first-level cache, and that an eviction of a cacheline from the third-level cache triggers the cache hierarchy control logic to evict a copy of that cacheline from the first-level cache when the cacheline is not present in the second-level cache.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: January 7, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Paul Moyer
  • Patent number: 10521132
    Abstract: A method for managing volumes in a scratch pool of a virtual tape system is disclosed. In one embodiment, such a method provides a scratch pool containing volumes for use in a virtual tape system. The method further enables a user to predefine an external pool of volumes residing outside of the scratch pool. This external pool may be hidden to a host system accessing the virtual tape system. The method monitors current and/or past usage of the volumes in the scratch pool and, based on the usage, predicts a future need for volumes in the scratch pool. The method automatically moves volumes between the external pool and the scratch pool in accordance with the future need. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: June 17, 2018
    Date of Patent: December 31, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael R. Scott, David C. Reed, Sosuke Matsui, Derek L. Erdmann