Abstract: In data transmitting systems, an apparatus for synchronizing the frame clock in units/nodes. The apparatus has a phase detector and a voltage controlled oscillator. At least one input of the phase detector is supplied with an incoming clock signal and another input is supplied with an output signal of the voltage controlled oscillator. The output signal of the voltage controlled oscillator is conducted over a divider, which is connected to a frame clock phase detector for setting its division factor. The frame clock phase detector is supplied with an input frame clock, the output of the variable divider, and at least one output of an output divider. The at least one output of the output divider divides the output signal of the controlled oscillator into the output frame clock. The frame clock phase detector is configured for the output of a pulse that temporarily raises or lowers the division factor of the divider when the phase difference between input and output clock deviates from a prescribable quantity.

Abstract: A feed-forward symbol synchronizer (200, FIG. 2) samples symbols transmitted within one or more packets that form a burst of radio frequency (RF) energy. The symbol samples (209) are delayed in a data delay buffer (214) while a phase estimate (212) is generated for each packet. A resampler (218) resamples the delayed symbol samples based on the phase estimate, resulting in resampled data (228) that includes one sample per symbol. The resampled data is clocked into a dual-port RAM (230) using a resampling clock that is also based on the phase estimate. The resampled data is then clocked out of the dual-port RAM and into a demodulator (238) using the receiver's symbol clock (232). Also described are methods of operating the feed-forward symbol synchronizer.