Abstract: This publication discloses a method for manufacturing an electronic module, in which manufacture commences from an insulating-material sheet (1). At least one recess (2) is made in the sheet (1) and extends through the insulating-material layer (1) as far as the conductive layer on the opposite surface (1a). A component (6) is set in the recess, with its contact surface towards the conductive layer and the component (6) is attached to the conductive layer. After this, a conductive pattern (14) is formed from the conductive pattern closing the recess, which is electrically connected from at least some of the contact areas or contact protrusions of the component (6) set in the recess.

Abstract: Provided are a resistive memory device having a probe array and a method of manufacturing the same. The resistive memory device includes a memory part having a bottom electrode and a ferroelectric layer sequentially formed on a first substrate; a probe part having an array of resistive probes arranged on a second substrate, with the tips of the resistive probes facing the ferroelectric layer so as to write and read data on the ferroelectric layer; and a binding layer which grabs and fixes the resistive probes on or above the ferroelectric layer. The method of manufacturing the resistive memory device includes forming a bottom electrode and a ferroelectric layer sequentially on a first substrate; forming an array of resistive probes on a second substrate; and wafer level bonding the first substrate to the second substrate using a binding layer such that tips of the resistive probes face the ferroelectric layer.

Abstract: A method for fabrication and a structure of a self-aligned (crosspoint) memory device comprises lines (wires) in a first direction and in a second direction. The wires in the first direction are formed using a hard mask material that is resistant to the pre-selected etch processes used for creation of the lines in both the first and the second direction. Consequently, the hard mask material for the lines in the first direction form part of the memory stack.

Abstract: A functional molecular device displaying its functions under the action of an electrical field is provided. A Louis base molecule, exhibiting positive dielectric constant anisotropy or exhibiting dipole moment along the long-axis direction of the Louis base molecule, is arrayed in the form of a pendant on an electrically conductive linear or film-shaped principal-axis molecule of a conjugated system, via a metal ion capable of acting as a Louis acid. The resulting structure is changed in conformation on application of an electrical field to exhibit its function. The electrically conductive linear or film-shaped principal-axis molecule and the Louis base molecule form a complex with the metal ion. On application of the electrical field, the Louis base molecule performs a swinging movement or a seesaw movement to switch the electrical conductivity of the principal-axis molecule.

Abstract: A phase-change memory device more precisely controls electrical current required to accomplish a phase change by using contact holes that extend between phase change layers that are sized differently from each other.

Abstract: The methods described herein relate to deposition of low resistivity, highly conformal tungsten nucleation layers. These layers serve as a seed layers for the deposition of a tungsten bulk layer. The methods are particularly useful for tungsten plug fill in which tungsten is deposited in high aspect ratio features. The methods involve depositing a nucleation layer by a combined PNL and CVD process. The substrate is first exposed to one or more cycles of sequential pulses of a reducing agent and a tungsten precursor in a PNL process. The nucleation layer is then completed by simultaneous exposure of the substrate to a reducing agent and tungsten precursor in a chemical vapor deposition process. In certain embodiments, the process is performed without the use of a borane as a reducing agent.

Abstract: Methods and structures provide a shielded multi-layer package for use with multi-chip modules and the like. A substrate (102) (e.g., chip carrier) has an adhesive layer (104), where electronic components (106, 108) are attached. An insulating layer (110) is formed over the plurality of electronic components, and a conductive encapsulant structure (115) is formed over the insulating layer. The adhesive layer is detached from the electronic components, and multi-layer circuitry (140) is formed over, and in electrical communication with, the plurality of electronic components. A shielding via (150) is formed through the multilayer circuitry such that it contacts the conductive encapsulant.

Abstract: A manufacturing method of a solid-state imaging device includes: forming a first and second insulating films having different properties on a silicon substrate such that they cover sides of gate electrodes formed on the silicon substrate; subjecting the second insulating film to selective etching, and forming sidewalls on the sides of the gate electrode; subjecting the gate electrode having the sidewalls formed to ion implantation; covering the gate electrode having the sidewalls formed and forming a third insulating film on the silicon substrate; covering with a mask material part of the gate electrodes covered with the third insulating film, and subjecting the substrate to etching to remove exposed third insulating film; and, after removing the mask material, forming a metal film capable of forming a silicide on the silicon substrate such that the metal film covers the gate electrodes and the third insulating film to form a silicide layer.

Abstract: A vertical semiconductor device comprises a semiconductor body, a first contact and a second contact, wherein a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and a third semiconductor region of a second conductivity type are formed in the semiconductor body in a direction from the first contact to the second contact, wherein a basic doping density of the second semiconductor region is smaller than a doping density of the third semiconductor region, and wherein in the second semiconductor region a semiconductor zone of the second conductivity type is arranged in which the doping density is increased relative to the basic doping density of the second semiconductor region.

Abstract: A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.

Abstract: A method for aligning a reticle is provided. A first patterned layer with a first alignment grid is formed. Sidewall layers are formed over the first patterned layer to perform a first shrink. The first alignment grid after shrink is etched into an etch layer to form an etched first alignment grid. The patterned layer is removed. An optical pattern of a second alignment grid aligned over the etched first alignment grid is measured. The optical pattern is used to determine whether the second alignment grid is aligned over the etched first alignment grid.

Abstract: A method of irradiating at least a part of a semiconductor film on the substrate with a CW or pseudo-CW laser beam so as to grow crystals laterally. A region over the semiconductor film having Si as a chief component is provided with a pixel region, a gate line driving circuit region and a signal line driving circuit region for driving pixels, and a terminal region where connection terminals will be formed. The region not irradiated with the CW laser beam is provided in a peripheral portion of each semiconductor device corresponding to the position where the glass substrate will be cut. Due to this means, it is possible to suppress occurrence of a failure caused by propagation of cracks when the substrate is cut.

Abstract: A system that facilitates precise inter-chip alignment. The system includes a first integrated circuit chip, whose surface has etch pit wells. The system also includes a second integrated circuit chip, whose surface has corresponding etch pit wells that mate with the etch pit wells of the first integrated circuit chip. Spherical balls are placed in the etch pit wells of the first integrated circuit chip such that when the corresponding etch pit wells of the second integrated circuit chip are substantially aligned with the spherical balls, the spherical balls mate with the etch well pits of the second integrated circuit chip, thereby precisely aligning the first integrated circuit chip with the second integrated circuit chip.

Abstract: A 3-T buried-gated photodiode device that is suitable for use in a windowed array. The 3-T buried-gated photodiode device is configured such that the floating diffusion (FD) node of the device is held low when the device is not being specifically addressed, which ensures that the device cannot drive the corresponding pixel output line unless it is specifically addressed.

Abstract: Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.

Abstract: The present invention provides in one embodiment a light emitting device that has a high efficacy even in a range of low color temperatures, a long-term reliability, and an improved color rendering property. In addition, the present invention provides in another embodiment a lighting apparatus using such a light emitting device. In the light emitting device, a mixture of a first phosphor material that emits yellow green, yellow or yellow orange light and a second phosphor material that emits light having a longer wavelength than the first phosphor material, for example, yellow orange or orange light is used as a phosphor. The first phosphor material is represented by a general formula Cax(Si, Al)12(O, N)16:Euy2+ and a main phase thereof has an alpha-SiAlON crystal structure.

Abstract: The present invention is directed to different methods used in the formation of an ink, as well as being directed to the formation of layers used in the fabrication of a solar cell, particularly the absorber layer. In one embodiment, the invention is directed to formulating an ink comprising Cu-rich particles and solid Ga—In particles, wherein the step of formulating is carried out at a temperature such that no liquid phase is present within the solid Ga-In particles. In another embodiment, the specific steps taken during the formulation of the ink are described. In yet another embodiment, the process of using the formulated ink to obtain a precursor layer are described.

Abstract: Provided is a new design and fabrication of scratch drive actuator (SDA) micro rotary motor with low driving voltage and high lifetime characteristics. To substantially reduce the driving voltage from 30˜150 Vo-p to 12˜30 Vo-p ac amplitude, a silicon wafer with very low resistivity (<0.004 ?-cm) was firstly adopted as the substrate of SDA micro motor. Furthermore, a novel SDA structure and geometric design for the improvement of lifetime (>75 hrs) and rotational speed (˜30 rpm) of SDA micro motor was also demonstrated in this patent.

Abstract: An image sensor and related method of fabrication are disclosed. The image sensor comprises a plurality of photoelectric conversion regions disposed in a predetermined field of a semiconductor substrate, color filters arranged on the photoelectric conversion regions, and a reflection protection structure disposed between the photoelectric conversion regions and the color filters. The reflection protection structure comprises portions having different thicknesses in relation to the color filters.

Abstract: A light-emitting device (200) has a submount (100) and a plate for heat transfer (300) having a metallic plate (30). The submount (100) has a mount base (10), at least one light-emitting diode chip (5) mounted thereon and electrically conducting lines (12-17) formed on the mount base (10) to be connected electrically to the light-emitting diode chip (5). A first plane (11) of the mount base (10) of the submount (100) is bonded thermally to the first plate (300). For example, the plate is a circuit board having a metallic plate (30), and the submount (100) is bonded thermally to the metallic plate (30) of the one of the at least one plate (300). In an example, a second plate for heat transfer is also bonded thermally to a second plane of the mount base (100) for providing a plurality of heat transfer paths.