Abstract: An accelerator may include one or more data processing units that perform deep learning operations in neural networks. A data processing unit includes a memory and a compute engine. The memory may include memory banks and clock domain crossing (CDC) buffers. Each memory bank may have its own CDC buffer(s). The memory banks may be grouped into bank groups. The memory may also include a group selection module and bank selection modules, each of which is associated with a different bank group. The group selection module may select a bank group for a data transfer request from the compute engine. The bank selection module of the selected bank group may select a memory bank from the selected bank group and store the data transfer request in a CDC buffer of the selected memory bank. The data transfer request may be transmitted to the selected memory bank from the CDC buffer.

Abstract: Examples described herein relate to a network interface device comprising an interface to memory and circuitry. In some examples, the circuitry is to: determine a number of data units stored in a page in the memory and based on no data unit stored in a page of memory, permit storage of a data unit in the page in the memory.

Abstract: An example of an apparatus may include memory, two or more caches, and circuitry coupled to the memory and the two or more caches to selectively maintain coherency of data shared among the memory and the two or more caches based on coherency bypass information associated with the data. Other examples are disclosed and claimed.

Abstract: Systems, methods, and apparatus for a memory device that stores a scrub list in a cache used to reduce data traffic to and from a memory array. In one approach, the cache merges the scrub list with cache data. Data in the scrub list can be identified and distinguished from the cache data by adding a one-bit scrub flag to each data entry in the merged cache. In this merged approach, the cache data shares the same memory as the scrub list. Read data that has an error is saved temporarily in this merged cache until the correct value for the data is written back into the memory array.

Abstract: A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, the metadata may be mapped to the data based on a portion of a column address. In some examples, whether the memory device provides metadata responsive to a column address may be based on a value stored in a mode register. In some examples, the portion of the column plane associated with the one column select associated with metadata may also store error correction code data associated with the data of the remaining column selects.

Abstract: Methods and apparatus for storing data and metadata in a storage network. In a method, one or more processing modules of a storage network establishes a vault as a virtual memory block that maps to memory of the storage network. The method further includes receiving data for storage in the vault, selecting a first vault parameter set regarding distributed storage of the data, and encoding at least a portion of the data in accordance with the first vault parameter set to produce a set of encoded data slices. The method further includes obtaining metadata regarding the set of encoded data slices, selecting a second vault parameter set regarding distributed storage of the metadata, and encoding the metadata in accordance with the second vault parameter set to produce metadata encoded slices. The method further includes facilitating storage of the set of encoded slices and the metadata encoded slices in the vault.

Abstract: Provided is a method for operating a memory device including performing a first setting operation on a first operation, reading map data based on the first setting operation, and performing a second setting operation on a second operation.

Abstract: Apparatuses, systems, and techniques to allocate portions of a virtual address space to allow virtual machines to share data. In at least one embodiment, at least a portion of a virtual memory address space is made accessible to multiple virtual machines and is mapped to memory addresses of different physical devices using, at least in part, a cache-coherent protocol.

Abstract: In a ray tracer, a cache for streaming workloads groups ray requests for coherent successive bounding volume hierarchy traversal operations by sending common data down an attached data path to all ray requests in the group at the same time or about the same time. Grouping the requests provides good performance with a smaller number of cache lines.

Abstract: A method includes receiving a first request to allocate a line in an N-way set associative cache and, in response to a cache coherence state of a way indicating that a cache line stored in the way is invalid, allocating the way for the first request. The method also includes, in response to no ways in the set having a cache coherence state indicating that the cache line stored in the way is invalid, randomly selecting one of the ways in the set. The method also includes, in response to a cache coherence state of the selected way indicating that another request is not pending for the selected way, allocating the selected way for the first request.

Abstract: A target virtual address is translated to a target physical address for a memory access request. At least for write requests, the memory access request is rejected when a target stage-1 translation table entry specifies that a target memory region corresponding to the target virtual address is a guarded control stack (GCS) region for storing a GCS data structure for protecting return state information, and the memory access request is not a GCS memory access request triggered by one of a restricted subset of GCS-accessing instruction types. When an anti-aliasing property is specified for the target memory region and the target stage-1 translation table entry or another stage-1 translation table entry used to locate the target stage-1 translation table entry is an unhardened entry unprotected by a translation hardening mechanism, the memory access request is rejected.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to forward and invalidate inflight data in a store queue. An example apparatus includes a cache storage, a cache controller coupled to the cache storage and operable to receive a first memory operation, determine that the first memory operation corresponds to a read miss in the cache storage, determine a victim address in the cache storage to evict in response to the read miss, issue a read-invalidate command that specifies the victim address, compare the victim address to a set of addresses associated with a set of memory operations being processed by the cache controller, and in response to the victim address matching a first address of the set of addresses corresponding to a second memory operation of the set of memory operations, provide data associated with the second memory operation.

Abstract: Methods, systems, and computer-readable storage media for storing, within a cache, a set of P byte arrays, a first byte array representing a map of a first plurality of entities of a first tenant associated with M entities, where M>P>1 and the set of P byte arrays are indexed by tenant and group identifier pairs, receiving a first request, the first request associated with a first entity, for the first entity, retrieving, from the cache, the first byte array by indexing at least a first subset of the P byte arrays using a tenant identifier of the first tenant and a first group identifier from a set of first group identifiers, generating a first map from the first byte array, the first map comprising first metadata that defines properties and logic associated with the first entity, and processing at least a portion of the first request using the first metadata.

Abstract: An example of an apparatus may include a first cache organized as two or more portions, a second cache, and circuitry coupled to the first cache and the second cache to determine a designated portion allocation for data transferred from the first cache to the second cache, and track the designated portion allocation for the data transferred from the first cache to the second cache. Other examples are disclosed and claimed.

Abstract: A storage device may include a non-volatile memory configured to store one file as a plurality of file fragments, and a storage controller configured to receive a read command with respect to the plurality of file fragments from a host through UFS protocol information unit (UPIU), and perform prefetching on the plurality of file fragments based on file fragmentation information included in an extra header segment (EHS) field of the UPIU.

Abstract: The present disclosure relates to methods and apparatuses for managing a shared cache. One example method includes determining an access characteristic of accessing the shared cache by IO requests of each of K types that access the shared cache, determining a partition size and an eviction algorithm of the IO requests of each type in the shared cache based on the determined access characteristic and a hit rate of the shared cache, and configuring a cache size of the IO requests of each type in the shared cache as the determined partition size, and configuring an eviction algorithm of the IO requests of each type in the shared cache as the determined eviction algorithm.

Abstract: Disclosed are a memory and operation method thereof. The memory comprises a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line. The method comprises: starting a specified random-column-access mode, in which the memory array can be continuously read or written in response to receiving multiple access addresses having a same row address and random column addresses; receiving a common row address and at least one column address via the data/address multiplexing line; outputting data read in response to the received access address via the data/address multiplexing line in the case where the mode indicates read operation, or receiving data to be written in response to the received access address via the data/address multiplexing line in the case where the mode indicates write operation; and ending the random column access mode by receiving an invalid chip-enable-signal.

Abstract: Implementations described herein relate to memory device hardware host read actions based on lookup operation results. In some implementations, a memory device may include one or more components configured to receive, by a hardware component of the one or more components and from a host device, a request to read data. The hardware component may be configured to perform a first lookup operation to determine whether the data is associated with a write data entry in a cache memory. The hardware component may be configured to perform a second lookup operation associated with an address of the data in a memory, where the second lookup operation is performed irrespective of a first result of the first lookup operation. The hardware component may be configured to perform one or more actions based on the first result and a second result of the second lookup operation.

Abstract: Systems, apparatuses, and methods related to storage device operation orchestration are described. A plurality of computing devices (or “tiles”) can be coupled to a controller (e.g., an “orchestration controller”) and an interface. The controller can control operation of the computing devices. For instance, the controller can include circuitry to request a block of data from a memory device coupled to the apparatus, cause a processing unit of at least one computing device of the plurality of computing devices to perform an operation on the block of data in which at least some of the data is ordered, reordered, removed, or discarded, and cause, after some of the data is ordered, reordered, removed, or discarded, the block of data to be transferred to the interface coupled to the plurality of computing devices.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.