Abstract: A method, computer program product, and computing system for defining a plurality of IO processing queues within a storage system coupled to a storage platform, wherein the plurality of IO processing queues have differing priority levels; receiving one or more IO requests on the storage system coupled to the storage platform; assigning the one or more IO requests to one or more of the plurality of IO processing queues based, at least in part, upon a priority level of the one or more IO requests; and servicing the plurality of IO processing queues in a distributed fashion.

Abstract: The methods and systems described herein provide a solution for protecting configuration data associated with a virtual private cloud. Network configurations, accounts, and/or security data may be collected from the host of the virtual private network using APIs provided by the host. The point-in-time configuration information of a VPC can be used in disaster recovery, migration to a new VPC host, or manage VPC configurations across accounts and regions. During a backup operation of a computing resource within a VPC, one or more processes requests security, network, and/or gateway configuration information from the VPC host. This information may be collected and requested for the entire VPC topology. The VPC configuration information, in the format/output received from the VPC host, is then backed up and stored with the backup of that computing resource in secondary storage.

Abstract: Techniques for data deduplication compress and deduplicate a first set of blocks written to a source system to obtain a second set of blocks and compression ratios and numbers of duplications for blocks in the second set of blocks. Such techniques receive a request to back up the first set of blocks. Such techniques reconstruct, in response to receiving the request to back up the first set of blocks, the second set of blocks to obtain the first set of blocks. Such techniques mark, based on the compression ratios and the numbers of duplications, blocks in the first set of blocks with deduplication flags to obtain a third set of blocks. Such techniques transmit the third set of blocks to a destination system.

Abstract: A storage device includes; a first memory subsystem including a first nonvolatile memory device (NVM), a first storage controller configured to control operation of the first NVM, and a first resource, and a second memory subsystem including a second NVM, a second storage controller configured to control operation of the second NVM, and a second resource, wherein the first resource is a shared resource useable by the second memory subsystem, and the second resource is shared resource useable by the first memory subsystem.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support enhanced exclusive access fairness operations for scalable exclusive monitor architectures. In a first aspect, device includes a processing system that includes one or more shared memory devices and one or more request nodes. The processing system also includes one or more network interface units (NIUs), each NIU including an exclusive monitor configured to monitor exclusive accesses to shared memory addresses for a corresponding request node and including a timeout register for the exclusive monitor configured to control exclusive access fairness. The processing system includes one or more home nodes coupled to a corresponding shared memory device of the one or more shared memory devices. The processing system further includes an interconnect configured to couple the one or more request nodes to the one or more shared memory devices. Other aspects and features are also claimed and described.

Abstract: Systems, methods, and computer readable media for tracking memory deltas at a cache line granularity. The method includes receiving a base address for a physical memory region, receiving a list of empty log memory buffers associated with a delta logging session, and responsive to determining that a cache line associated with the physical memory region may be in a modified state, storing the modified cache line and metadata associated with the modified cache line in an active log memory buffer referenced by the list of empty log memory buffers. The method also includes determining that the active log memory buffer is full and appending a flag to the active log memory buffer, thereby marking the active log memory buffer as a full log memory buffer. The method also includes storing a list of full log memory buffers, wherein the list is visible to a host processor.

Abstract: Instead of a system with no awareness to the specific properties of the described system files, such as atomicity of different types of system files, utilize the special characteristics of the corresponding system files to optimize storage handling. A host marks a certain logical block address (LBA) range as belonging to an atomic file. That entire range will be treated as a single atomic unit. Conversely, an LBA range being used to append to a log file may have very small atomic units, allowing for incremental updates without changing the atomicity of the rest of the media. When a write command is passed, the write command will have a certain length. Depending on the length of the write command, the device can disassemble the write command into smaller write sectors of the smallest possible write portion. The device will then write the small write portions to a storage location, while keeping an atomic principle of each of the small write portions.

Abstract: For each data in a plurality of data, data is read from a cache unit. For each data in the plurality of data, a group to which the data read from the cache unit belongs to is determined based at least in part on a predetermined grouping rule. A determination is made of (1) a quantity of groups and (2) a quantity of data corresponding to each group after determining the groups to which the plurality of data belong. Data belonging to a same group is written into a contiguous storage space of the cache unit, including by: sequentially reading the plurality of data from the cache unit and sequentially writing the plurality of data into the cache unit.

Abstract: Methods, systems, and devices for enhanced data reliability in multi-level memory cells are described. For a write operation, a host device may identify a first set of data to be stored by a set of memory cells at a memory device. Based on a quantity of bits within the first set of data being less than a storage capacity of the set of memory cells, the host device may generate a second set of data and transmit a write command including the first and second sets of data to the memory device. For a read operation, the host device may receive a first set of data from the memory device in response to transmitting a read command. The memory device may extract a second set of data from the first set of data and validate a portion of the first set of data using the second set of data.

Abstract: A device for use in a storage network including storage network memory distributed amongst a plurality of storage units. The device includes a processing module operably couple to a memory that stores operational instructions. The processing module is configured to execute the operational instructions to determine storage parameters associated with encoded data slices generated from data to be stored in the plurality of storage units. The storage parameters include information indicating a read threshold number of encoded data slices required to recover the data. The method further includes facilitating distributed storage of the encoded data slices among the plurality of storage units such that the number of the error-encoded data slices stored in any particular storage unit is chosen so that in the event of an unavailability of any individual storage unit, at least a read threshold number of encoded data slices are still accessible from the remaining storage units.

Abstract: A caching system including a first sub-cache, and a second sub-cache, coupled in parallel with the first cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and wherein the second sub-cache includes: color tag bits configured to store an indication that a corresponding cache line of the second sub-cache storing write miss data is associated with a color tag, and an eviction controller configured to evict cache lines of the second sub-cache storing write-miss data based on the color tag associated with the cache line.

Abstract: The invention provides method and system for improving efficiency of protecting multi-content process. The system may cooperate with a memory, and may comprise one or more hardware IPs (intellectual properties) for content processing, one of the one or more IPs may be associated with multiple access identities. The memory may comprise multiple different ranges, each range may register an access of one of the multiple access identities as a permissible access. The method may comprise: selecting one of the access identities for processing a first content, and using the selected access identity when said IP accesses the memory during processing of the first content; selecting a different one of the access identities for processing a second content, and using the selected different access identity when said IP accesses the memory during processing of the second content.

Abstract: An apparatus including memory access circuitry for controlling access to data stored in the non-trusted memory, and memory security circuitry to verify integrity of data stored in the non-trusted memory. The memory security circuitry has authentication code generation circuitry for generating authentication codes to be associated with the data stored in the non-trusted memory, for use when verifying the integrity of the data. The apparatus also has a trusted storage, and the authentication code generation circuitry is arranged to generate different authentication codes, dependent on whether the authentication code is to be stored in the non-trusted memory or the trusted storage.

Abstract: Transaction mappers, methods and systems are provided. An example transaction mapper includes a table that associates virtual identification values with bus-device-function (BDF) values; and a firewall that receives an input-output request including a first virtual identification value of the virtual identification values, the first virtual identification value being associated with a function of an external peripheral, generates a first BDF value and a first traffic class value based on the table and the first virtual identification value, determine whether the first virtual identification value satisfies a threshold range, and determine whether to forward the input-output request to an external host device based on whether the first virtual identification value satisfies the threshold range.

Abstract: Handling frequently accessed pages is disclosed. An indication is received of a stalling event caused by a requested portion of memory being inaccessible. It is determined that the requested portion of memory is a frequently updated portion of memory. The stalling event is handled based at least in part on the determination that the requested portion of memory is a frequently updated portion of memory.

Abstract: A hardware-assisted Distributed Memory System may include software configurable shared memory regions in the local memory of each of multiple processor cores. Accesses to these shared memory regions may be made through a network of on-chip atomic transaction engine (ATE) instances, one per core, over a private interconnect matrix that connects them together. For example, each ATE instance may issue Remote Procedure Calls (RPCs), with or without responses, to an ATE instance associated with a remote processor core in order to perform operations that target memory locations controlled by the remote processor core. Each ATE instance may process RPCs (atomically) that are received from other ATE instances or that are generated locally. For some operation types, an ATE instance may execute the operations identified in the RPCs itself using dedicated hardware. For other operation types, the ATE instance may interrupt its local processor core to perform the operations.

Abstract: Provided is a method for operating a memory device including performing a first setting operation on a first operation, reading map data based on the first setting operation, and performing a second setting operation on a second operation.

Abstract: A method and apparatus for generating a histogram includes receiving an input key, determining if a linked-list node associated with the input key exists in the linked-list memory, in response to determining that a linked-list node associated with the input key does exist in the linked-list memory, increasing at least one count stored in the linked-list node associated with the input key, in response to determining that a linked-list node associated with the input key does not exist in the linked-list memory, determining if an available slot exists in the key storage memory, in response to determining that an available slot does not exist in the key storage memory determining a reclaimed slot in the key storage memory and a reclaimed node in the linked-list memory that is associated with the reclaimed slot, transmitting the data stored in the reclaimed slot in the key storage memory and the at least one count associated with the data stored in the reclaimed slot to an external device, and storing the key inpu

Abstract: According to one embodiment, a controller creates a virtual controller based on an attached state of the namespace with respect to the storage area of the nonvolatile memory based on reception of a first command requesting connection from a first host. The controller executes processing related to an operation of the namespace requested by a second command related to the operation of the namespace based on an attached state of the namespace in the virtual controller when the second command is received from the first host.

Abstract: A system includes a multi-core shared memory controller (MSMC). The MSMC includes a snoop filter bank, a cache tag bank, and a memory bank. The cache tag bank is connected to both the snoop filter bank and the memory bank. The MSMC further includes a first coherent slave interface connected to a data path that is connected to the snoop filter bank. The MSMC further includes a second coherent slave interface connected to the data path that is connected to the snoop filter bank. The MSMC further includes an external memory master interface connected to the cache tag bank and the memory bank. The system further includes a first processor package connected to the first coherent slave interface and a second processor package connected to the second coherent slave interface. The system further includes an external memory device connected to the external memory master interface.