Abstract: A method includes receiving a first request to allocate a line in an N-way set associative cache and, in response to a cache coherence state of a way indicating that a cache line stored in the way is invalid, allocating the way for the first request. The method also includes, in response to no ways in the set having a cache coherence state indicating that the cache line stored in the way is invalid, randomly selecting one of the ways in the set. The method also includes, in response to a cache coherence state of the selected way indicating that another request is not pending for the selected way, allocating the selected way for the first request.

Abstract: A target virtual address is translated to a target physical address for a memory access request. At least for write requests, the memory access request is rejected when a target stage-1 translation table entry specifies that a target memory region corresponding to the target virtual address is a guarded control stack (GCS) region for storing a GCS data structure for protecting return state information, and the memory access request is not a GCS memory access request triggered by one of a restricted subset of GCS-accessing instruction types. When an anti-aliasing property is specified for the target memory region and the target stage-1 translation table entry or another stage-1 translation table entry used to locate the target stage-1 translation table entry is an unhardened entry unprotected by a translation hardening mechanism, the memory access request is rejected.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to forward and invalidate inflight data in a store queue. An example apparatus includes a cache storage, a cache controller coupled to the cache storage and operable to receive a first memory operation, determine that the first memory operation corresponds to a read miss in the cache storage, determine a victim address in the cache storage to evict in response to the read miss, issue a read-invalidate command that specifies the victim address, compare the victim address to a set of addresses associated with a set of memory operations being processed by the cache controller, and in response to the victim address matching a first address of the set of addresses corresponding to a second memory operation of the set of memory operations, provide data associated with the second memory operation.

Abstract: Methods, systems, and computer-readable storage media for storing, within a cache, a set of P byte arrays, a first byte array representing a map of a first plurality of entities of a first tenant associated with M entities, where M>P>1 and the set of P byte arrays are indexed by tenant and group identifier pairs, receiving a first request, the first request associated with a first entity, for the first entity, retrieving, from the cache, the first byte array by indexing at least a first subset of the P byte arrays using a tenant identifier of the first tenant and a first group identifier from a set of first group identifiers, generating a first map from the first byte array, the first map comprising first metadata that defines properties and logic associated with the first entity, and processing at least a portion of the first request using the first metadata.

Abstract: An example of an apparatus may include a first cache organized as two or more portions, a second cache, and circuitry coupled to the first cache and the second cache to determine a designated portion allocation for data transferred from the first cache to the second cache, and track the designated portion allocation for the data transferred from the first cache to the second cache. Other examples are disclosed and claimed.

Abstract: A storage device may include a non-volatile memory configured to store one file as a plurality of file fragments, and a storage controller configured to receive a read command with respect to the plurality of file fragments from a host through UFS protocol information unit (UPIU), and perform prefetching on the plurality of file fragments based on file fragmentation information included in an extra header segment (EHS) field of the UPIU.

Abstract: The present disclosure relates to methods and apparatuses for managing a shared cache. One example method includes determining an access characteristic of accessing the shared cache by IO requests of each of K types that access the shared cache, determining a partition size and an eviction algorithm of the IO requests of each type in the shared cache based on the determined access characteristic and a hit rate of the shared cache, and configuring a cache size of the IO requests of each type in the shared cache as the determined partition size, and configuring an eviction algorithm of the IO requests of each type in the shared cache as the determined eviction algorithm.

Abstract: Disclosed are a memory and operation method thereof. The memory comprises a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line. The method comprises: starting a specified random-column-access mode, in which the memory array can be continuously read or written in response to receiving multiple access addresses having a same row address and random column addresses; receiving a common row address and at least one column address via the data/address multiplexing line; outputting data read in response to the received access address via the data/address multiplexing line in the case where the mode indicates read operation, or receiving data to be written in response to the received access address via the data/address multiplexing line in the case where the mode indicates write operation; and ending the random column access mode by receiving an invalid chip-enable-signal.

Abstract: Implementations described herein relate to memory device hardware host read actions based on lookup operation results. In some implementations, a memory device may include one or more components configured to receive, by a hardware component of the one or more components and from a host device, a request to read data. The hardware component may be configured to perform a first lookup operation to determine whether the data is associated with a write data entry in a cache memory. The hardware component may be configured to perform a second lookup operation associated with an address of the data in a memory, where the second lookup operation is performed irrespective of a first result of the first lookup operation. The hardware component may be configured to perform one or more actions based on the first result and a second result of the second lookup operation.

Abstract: Systems, apparatuses, and methods related to storage device operation orchestration are described. A plurality of computing devices (or “tiles”) can be coupled to a controller (e.g., an “orchestration controller”) and an interface. The controller can control operation of the computing devices. For instance, the controller can include circuitry to request a block of data from a memory device coupled to the apparatus, cause a processing unit of at least one computing device of the plurality of computing devices to perform an operation on the block of data in which at least some of the data is ordered, reordered, removed, or discarded, and cause, after some of the data is ordered, reordered, removed, or discarded, the block of data to be transferred to the interface coupled to the plurality of computing devices.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Abstract: Techniques for slicing memory of a hardware processor core by linear address are described.

Abstract: Apparatuses and methods of operating such apparatuses are disclosed, where the apparatus provides ring buffer storage to hold queued elements. Multiple head pointers are stored and maintained with respect to the ring buffer, wherein the multiple head pointers have a multiplicity N. When a dequeuing operation is performed with respect to an element queued in the ring buffer, reference is made to a selected head pointer of the multiple head pointers and a slot index value is derived. An element held in a slot corresponding to the slot index value is dequeued and the value of the selected head pointer is increased by N. Support for concurrent dequeuing operations is thus provided, in that write contention for a single head pointer is avoided.

Abstract: Methods, systems, and devices related to determining whether a target address of a memory array associated with an access request is stored in a CAM. If the target address is stored in the CAM, the CAM may be updated to increment an access count of a target row corresponding to the target address. If the target row exceeds a first threshold value, rows of the memory array directly adjacent to the target row may be refreshed. If the target address is not stored in the CAM, the target address may be written to the CAM. The CAM may be updated to increment an access count of an address of a bank including the target row corresponding to the target address.

Abstract: Disclosed is a dynamic random access memory (DRAM) that includes a plurality of data rows and a plurality of tag rows. The DRAM includes a communication interface to receive a first group of address bits. The DRAM includes one or more comparators to generate a tag match indication and one or more set bits based on the first group of address bits and a first group of tag information bits from the plurality of tag rows. The one or more comparators are further to combine, based on the tag match indication, the one or more set bits and the first group of address bits to generate a second group of address bits.

Abstract: A working-set structure is used to organize cached data for storing to persistent storage, which includes leaf structures and page descriptors (PDs) for data pages to be persisted. Upon adding a new PD located in an address range of an existing leaf structure, a PD population count of the existing leaf structure is compared to a predetermined PD population threshold. When the count is below the threshold, the new PD is incorporated into an existing set of PDs for the existing leaf structure, and otherwise (a) a new leaf structure is created, and (b) the new leaf structure is used for the new PD and later-added PDs in the address range. Flush parallelism is enhanced by avoiding large differences in PD population across a set of leaf structures.

Abstract: Implementations of the present application disclose a method of operating a memory controller, a device and a storage medium. The controller is coupled to the memory, and the method includes: acquiring respective lifetimes of at least two partitions included in the memory, the lifetimes of the partitions being related to wear levels of the partitions; determining a target partition from the at least two partitions based on the respective lifetimes of the at least two partitions; and selecting a block from the target partition as a temporary block, the temporary block to store fragmented data. The above method avoids excessive wear to a certain fixed partition in the memory caused by setting the temporary block, thereby improving the service life of the memory.

Abstract: Techniques are disclosed relating to private memory management using a mapping thread, which may be persistent. In some embodiments, a graphics processor is configured to generate a pool of private memory pages for a set of graphics work that includes multiple threads. The processor may maintain a translation table configured to map private memory addresses to virtual addresses based on identifiers of the threads. The processor may execute a mapping thread to receive a request to allocate a private memory page for a requesting thread, select a private memory page from the pool in response to the request, and map the selected page in the translation table for the requesting. The processor may then execute one or more instructions of the requesting thread to access a private memory space, wherein the execution includes translation of a private memory address to a virtual address based on the mapped page in the translation table.

Abstract: A storage device includes a nonvolatile semiconductor memory device including a plurality of physical blocks and a memory controller. The memory controller is configured to associate one or more physical blocks to each of a plurality of stream IDs, execute a first command containing a first stream ID received from a host, by storing write data included in the write IO in the one or more physical blocks associated with the first stream ID, and execute a second command containing a second stream ID received from the host, by selecting a first physical block that includes valid data and invalid data, transfer the valid data stored in the first physical block to a second physical block, and associate the first physical block from which the valid data has been transferred, with the second stream ID.

Abstract: This application is directed to managing errors on a memory device. The memory device includes non-volatile memory (NVM) storing data and dynamic random-access memory (DRAM) storing a logic-to-physical (L2P) table and a poison table. The memory device obtains a data access request to access a data item stored in the NVM, and the data access request includes a logical address of the data item. The memory device identifies, in the L2P table, a mapping entry corresponding to the logical address of the data item, and the mapping entry maps the logical address of the data item to a physical address of the data item within the NVM, and determines that the mapping entry has an uncorrectable error. In accordance with a determination that the mapping entry has the uncorrectable error, the memory device adds, in the poison table, an index identifying the mapping entry in the L2P table.