Patents Examined by Asok Unmar Sarkar
  • Method of forming transistors with self aligned damascene gate contact
    Patent number: 6291278
    Abstract: A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-K gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.
    Type: Grant
    Filed: May 3, 1999
    Date of Patent: September 18, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Qi Xiang, Matthew S. Buynoski, Ming-Ren Lin
  • Process for forming shaped group II-VI semiconductor nanocrystals, and product formed using process
    Patent number: 6225198
    Abstract: A process for the formation of shaped Group II-VI semiconductor nanocrystals comprises contacting the semiconductor nanocrystal precursors with a liquid media comprising a binary mixture of phosphorus-containing organic surfactants capable of promoting the growth of either spherical semiconductor nanocrystals or rod-like semiconductor nanocrystals, whereby the shape of the semiconductor nanocrystals formed in said binary mixture of surfactants is controlled by adjusting the ratio of the surfactants in the binary mixture.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: May 1, 2001
    Assignee: The Regents of the University of California
    Inventors: A. Paul Alivisatos, Xiaogang Peng, Liberato Manna
  • Sensor device and method of forming a sensor device
    Patent number: 6214634
    Abstract: A sensor device (20) comprises a sensor package (22) having a cavity (24) formed therein, a sensor die (26) mounted on a bottom surface (28) of the cavity (24) and a protective coating (30) formed over the sensor die in the cavity. The protective coating (30) is formed from a material, preferably a polymer material, which is arranged to have a graduated cross-linking density such that the material at the top of the cavity (24) has a high density of cross-linking and the material at the bottom of the cavity (24), which material is in contact with the sensor die, has a low density of cross-linking.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: April 10, 2001
    Assignee: Motorola, Inc.
    Inventors: Marc Osajda, Eric Perraud
  • Method for producing semiconductor base members
    Patent number: 6180497
    Abstract: A method of producing a semiconductor base member that can be used as a Silicon on Insulator (SOI) wafer is presented. To produce an SOI wafer, it is necessary to prepare a base member having a porous layer upon which a non porous layer is formed. To make the pore size distribution of a porous layer uniform, a surface comprising atom steps and terraces is formed on the surface of a silicon base material and made porous without eliminating the steps and terraces, and then a nonporous semiconductor single-crystal film is formed thereon.
    Type: Grant
    Filed: July 21, 1999
    Date of Patent: January 30, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuhiko Sato, Satoshi Matsumura