Patents Examined by Austin Hicks
  • Patent number: 10394311
    Abstract: An information processing apparatus includes a first processor and a second processor. The first processor is operable to perform first processing and second processing in one of a plurality of operating states. The operating states includes a normal state and a power-saving state. The power-saving state is a state in which the first processor consumes less power than the normal state. The second processor is operable to perform the second processing while consuming less power than the first processor does. The second processor detects the first processing that the second processor is not able to perform. The second processor also causes the first processor to transition from the sleep state to the power-saving state to perform the first processing when the first processor is in a sleep state in which a power supply is stopped.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: August 27, 2019
    Assignee: RICOH COMPANY, LTD.
    Inventor: Satoshi Tanaka
  • Patent number: 10395118
    Abstract: Described herein are systems and methods that exploit hierarchical Recurrent Neural Networks (RNNs) to tackle the video captioning problem; that is, generating one or multiple sentences to describe a realistic video. Embodiments of the hierarchical framework comprise a sentence generator and a paragraph generator. In embodiments, the sentence generator produces one simple short sentence that describes a specific short video interval. In embodiments, it exploits both temporal- and spatial-attention mechanisms to selectively focus on visual elements during generation. In embodiments, the paragraph generator captures the inter-sentence dependency by taking as input the sentential embedding produced by the sentence generator, combining it with the paragraph history, and outputting the new initial state for the sentence generator.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: August 27, 2019
    Assignee: Baidu USA LLC
    Inventors: Haonan Yu, Jiang Wang, Zhiheng Huang, Yi Yang, Wei Xu
  • Patent number: 10372460
    Abstract: An information handling system includes a data processor, a security co-processor, and a baseboard management controller (BMC). The security co-processor operates during a first in time portion of a boot process of the information handling system. The BMC provides first video display content during the first in time portion of the boot process. The data processor provides second video display content during a second in time portion of the boot process.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: August 6, 2019
    Assignee: Dell Products, LP
    Inventors: Timothy M. Lambert, Jeffrey L. Kennedy
  • Patent number: 10365702
    Abstract: Over at least part of a lifetime of a product circuit, quiescent current to a product circuit is periodically measured. Over the part of the lifetime of the product circuit, voltage to the product circuit is periodically adjusted based on the monitored quiescent current. Methods, apparatus, and computer program product are disclosed. A calibration procedure may also be performed as part of manufacturing the product circuit, in order to provide values for the quiescent current and corresponding voltage to which the voltage should be adjusted.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chen-Yong Cher, Pierce I Chuang, Keith A Jenkins, Barry Linder
  • Patent number: 10353425
    Abstract: A time information providing apparatus includes a power supply; a clock oscillator configured to generate a clock signal; a communicator configured to transmit a current-time information request to a content providing server or receive a current-time information response corresponding to the current-time information request from the content providing server via the network; a real-time clock (RTC) module configured to generate real-time information representing an actual time; and a controller configured to, in response to the power supply supplying power, control the clock oscillator to generate a clock signal, apply the clock signal to the RTC module, and control the communicator to transmit the current-time information request, and in response to the communicator receiving the current-time information response, control the RTC module to record current-time information based on the current-time information response, and control the RTC module to generate the real-time information by using the clock signal a
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: July 16, 2019
    Assignee: HANWHA TECHWIN CO., LTD.
    Inventor: Bonghyen Kwon
  • Patent number: 10353860
    Abstract: A neural network unit. A register holds an indicator that specifies narrow and wide configurations. A first memory holds rows of 2N/N narrow/wide weight words in the narrow/wide configuration. A second memory holds rows of 2N/N narrow/wide data words in the narrow/wide configuration. An array of neural processing units (NPU) is configured as 2N/N narrow/wide NPUs and to receive the 2N/N narrow/wide weight words of rows from the first memory and to receive the 2N/N narrow/wide data words of rows from the second memory in the narrow/wide configuration. In the narrow configuration, the 2N NPUs perform narrow arithmetic operations on the 2N narrow weight words and the 2N narrow data words received from the first and second memories. In the wide configuration, the N NPUs perform wide arithmetic operations on the N wide weight words and the N wide data words received from the first and second memories.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: July 16, 2019
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: G. Glenn Henry, Terry Parks
  • Patent number: 10339442
    Abstract: Systems and methods are disclosed for operating a Restricted Boltzmann Machine (RBM) by determining a corrected energy function of high-order semi-RBMs (hs-RBMs) without self-interaction; performing distributed pre-training of the hs-RBM; adjusting weights of the hs-RBM using contrastive divergence; generating predictions by Gibbs Sampling or by determining conditional probabilities with hidden units integrated out; and generating predictions.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: July 2, 2019
    Assignee: NEC Corporation
    Inventors: Renqiang Min, Eric Cosatto
  • Patent number: 10331196
    Abstract: A system and method for providing efficient clock gating capability for functional units are described. A functional unit uses a clock gating circuit for power management. A setup time of a single device propagation delay is provided for a received enable signal. When each of a clock signal, the enable signal and a delayed clock signal is asserted, an evaluate node of the clock gating circuit is discharged. When each of the clock signal and a second clock signal is asserted and the enable signal is negated, the evaluate node is left floating for a duration equal to the hold time. Afterward, the devices in a delayed onset keeper are turned on and the evaluate node has a path to the power supply. When the clock signal is negated, the evaluate node is precharged.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: June 25, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Russell Schreiber
  • Patent number: 10324731
    Abstract: The present invention provides a multimode startup method for intelligent device and the system thereof, through predefining a plurality of startup modes, and based on a plurality of application scenarios according to the application and service programs installed in the intelligent device, assigning the said application programs and service programs into different startup modes, then receiving a control instruction sent from the user, identifying the startup mode according to the said control instruction, before loading the application and service programs list assigned to the specific startup mode according to the identified startup mode.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: June 18, 2019
    Assignee: SHENZHEN SKYWORTH-RGB ELECTRONIC CO., LTD
    Inventor: Jinpeng Liu
  • Patent number: 10317986
    Abstract: A secondary side controller for a power converter configured to provide a control signal to an emitter element of an opto-coupler for control of a primary side controller of the power converter, the secondary side controller configured to operate with the primary side controller for controlling the voltage output of the power converter, the secondary side controller configured to, based on; a first control value configured to instruct the power converter to output its present voltage output; and a second control value configured to instruct the power converter to provide a requested target voltage output; provide said control signal in accordance with a transition profile over a predetermined transition time period to effect a change between the first control value and the second control value, the transition profile comprising at least a first rate of change in the control signal followed by an end time period leading to the end of the transition time period during which the rate of change in the control
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: June 11, 2019
    Assignee: NXP B.V.
    Inventors: Robert Henri de Nie, Wilhelmus Hinderikus Maria Langeslag, Peter Laro
  • Patent number: 10317982
    Abstract: The present disclosure includes apparatuses and methods for sequence power control. A number of embodiments include executing a number of sequences associated with a number of commands, wherein a number of logical unit (LUN) controllers execute the number of sequences by locating power consumption information and a starting address of the number of sequences stored in a data structure on the number of LUN controllers.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Laszlo Borbely-Bartis
  • Patent number: 10310866
    Abstract: An electronic device is provided such that a user can experience a quick launch of an application therein. The electronic device includes a housing, a display, an input unit, a processor, a non-volatile memory to store an application program, and a volatile memory to store instructions that allow the processor to load a first part of the application program in the volatile memory based on a first change of state of the electronic device, to load a second part of the application program in the volatile memory based on a second change of state of the electronic device and to display an image or text generated by the loaded first or second part. Since at least part of the application is preloaded before the second input is generated, only the remainder of the application has to be loaded in order to execute the application after the second input is generated.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: June 4, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Hyung Jung, Chang-Gue Lee, Taejin Hyeon, Hyunsoo Kim, Minho Kim, Jong-Wu Baek
  • Patent number: 10303241
    Abstract: One embodiment of the present invention provides a system for a fine-grained power management. The system receives, by a first server, a task assigned based on a global power state, wherein the first server includes one or more drives, a drive includes one or more channels, and a channel includes one or more integrated circuits. The system places an inactive drive into a power-saving mode. The system places an inactive channel of an active drive into the power-saving mode by using a power switch associated with each integrated circuit in the inactive channel. The system places an inactive integrated circuit of an active channel into the power-saving mode by using a power switch associated with the inactive integrated circuit. The system updates a data structure storing the global power state based on a current power state of the first server, the drives, the channels, and the integrated circuits.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: May 28, 2019
    Assignee: Alibaba Group Holding Limited
    Inventors: Shu Li, Ping Zhou
  • Patent number: 10296714
    Abstract: This invention provides a computer method and system for interactive administration of medical cannabinoid treatments. The invention also provides information on cannabinoid product availability and geographical information. Medical professionals, cannabis growers, cannabis manufacturers, and other stakeholders can use this computer method and system to study trends, efficacy, and other information pertinent to the medical cannabis market.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: May 21, 2019
    Assignee: Potbotics, Inc.
    Inventors: Boris Goldstein, David Goldstein, Milla Bakhareva
  • Patent number: 10296353
    Abstract: A method of protecting basic input/output system (BIOS) code. The method includes, with a relocation information tool executed by a processor, refactoring a number of data sections within a number of handlers of the BIOS code to tag a number of variables within the handlers. The tags indicate which of the variables should be protected at runtime. The method further includes generating a relocation file comprising a number of relocation addresses identifying locations of a number of dynamic variables that change at runtime. The relocation addresses point to a location within the handlers different from an original location. The method further includes, with a loader, loading at runtime the relocation file as part of a BIOS firmware image and adjusting data access to the dynamic variables in handler code to identify the location of the dynamic variables based on the relocation file.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: May 21, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Wei Ze Liu, Jeffrey Kevin Jeansonne, Dallas M Barlow
  • Patent number: 10296063
    Abstract: An apparatus is disclosed, including a monitoring circuit, a translation circuit, a first filter circuit, a second filter circuit, and an interface. The monitoring circuit may be configured to receive a plurality of code values indicative of a voltage level of a power supply signal. The translation circuit may be configured to translate a particular code value to a corresponding voltage value of a plurality of voltage values. The first filter circuit may be configured to filter one or more of the plurality of voltage values to generate a plurality of filtered voltage values. The second filter circuit may be configured to generate a plurality of current values using one or more of the plurality of filtered voltage values and based on an impulse response of the power supply signal. The interface may be configured to send one or more of the plurality of current values to a functional circuit.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 21, 2019
    Assignee: Oracle International Corporation
    Inventors: Yifan YangGong, Sebastian Turullols, Vijay Srinivasan
  • Patent number: 10289423
    Abstract: A system management controller with a consolidated memory is disclosed. The example computing device includes a processor to host an operating system and a system memory to be used by the processor to execute instructions. The computing device also includes a management controller to enable out-of-band management of the computing device. The management controller includes a consolidated memory device. A first memory block of the consolidated memory device is used by the management controller as a working memory and a second memory block of the consolidated memory device is used for long-term storage of programming instructions.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: May 14, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Vincent Nguyen, Chanh V. Hua, Ning Ge, Naveen Muralimanohar
  • Patent number: 10289190
    Abstract: Systems and methods are provided for managing power to devices in a network, using a centralized power allocation controller. The method of managing power consumption of a plurality of devices includes receiving scheduled upcoming calendar events and/or activities from one or more of a plurality of devices connected in a network. The method further includes centrally managing power consumption of a device of the plurality of devices in the network based on the scheduled upcoming calendar events and/or activities.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: May 14, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory J. Boss, Andrew R. Jones, P. Daniel Kangas, Kevin C. McConnell, John E. Moore, Jr.
  • Patent number: 10282226
    Abstract: Techniques for optimizing CPU usage in a host system based on VM guest OS power and performance management are provided. In one embodiment, a hypervisor of the host system can capture information from a VM guest OS that pertains to a target power or performance state set by the guest OS for a vCPU of the VM. The hypervisor can then perform, based on the captured information, one or more actions that align usage of host CPU resources by the vCPU with the target power or performance state.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: May 7, 2019
    Assignee: VMWARE, INC.
    Inventors: Andrei Warkentin, Cyprien Laplace, Regis Duchesne, Ye Li, Alexander Fainkichen
  • Patent number: 10275394
    Abstract: A processor has an instruction fetch unit that fetches ISA instructions from memory and execution units that perform operations on instruction operands to generate results according to the processor's ISA. A hardware neural network unit (NNU) execution unit performs computations associated with artificial neural networks (ANN). The NNU has an array of ALUs, a first memory that holds data words associated with ANN neuron outputs, and a second memory that holds weight words associated with connections between ANN neurons. Each ALU multiplies a portion of the data words by a portion of the weight words to generate products and accumulates the products in an accumulator as an accumulated value. Activation function units normalize the accumulated values to generate outputs associated with ANN neurons. The ISA includes at least one instruction that instructs the processor to write data words and the weight words to the respective first and second memories.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: April 30, 2019
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: G. Glenn Henry, Terry Parks