Abstract: An information processing network includes multiple processing devices, a main storage memory, and an interface coupling the processing devices to the main storage memory. All processing devices contend for control of the interface on an equal basis, subject to a dynamically shifting sequence of priority rankings, invoked to resolve contentions for the interface or for one of a plurality of hardware class locks. The class locks are uniquely associated with different capabilities or classes of data operations, which reduces the number of contentions and allows multiple operations to proceed simultaneously. Arbitration logic encompassing all of the processing devices is duplicated in each of the processing devices, and kept coherent through an interconnection of multiple data buses. One bus is associated with each processing device, receives the output of the associated processing device and provides the output to each of the other processing devices.

Abstract: An arithmetic and logic processor includes a register file structure wherein each procedure to be processed has assigned thereto a predetermined number of registers referred to as register window. The processor further includes circuitry for comparing a predetermined constant LENGTH with the difference between the register window currently utilized by a procedure under execution and the base address of the register file, and circuitry responsive to the comparing circuitry output to detect when data should be transferred on a window basis to or from the register file from or to a stack memory for saving the register file contents, and circuitry responsive to the decision circuitry output to perform data transfer between the register file and the stack memory. According to such circuitry, overflow and underflow of the register file can be greatly suppressed to improve processing speed of the processor.