Patents Examined by Ayaz R. Sheiki
  • Patent number: 6088751
    Abstract: The present invention comprises a computer system with a reconfigurable bus priority arbitration system. The computer system of the present invention includes a master device, a slave device, an arbiter and a reconfigurable bus priority arbitration system, all coupled to a bus. The reconfigurable arbitration system determines said master device's relative priority for bus accesses and is capable of implementing a plurality of linked arbitration priority schemes.
    Type: Grant
    Filed: February 12, 1998
    Date of Patent: July 11, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: Kenneth Jaramillo