Abstract: A CPU mode switching circuit without a mode switching terminal includes a power on reset circuit generating a power on reset signal when circuit power is turned on, a reset signal generating circuit coupled to the power on reset circuit for receiving the power on reset signal and an external reset signal terminal for receiving an external reset signal. The reset signal generating circuit outputs an internal reset signal in response to the received signals. The CPU mode switching circuit further includes a CPU mode selector having operation mode data as internal data thereof and a CPU coupled to the CPU mode selector and the reset signal generating circuit. The CPU mode selector resets the internal data in response to the power on reset signal. The CPU changes the operation mode according to the internal data of the CPU mode selector when the CPU receives the internal reset signal. Then, the CPU rewrites the internal data of the CPU mode selector.

Abstract: A multitasking data processing system for executing a plurality of processes is provided that includes a single peripheral device addressable through two ports. A peripheral device manager is provided that includes the capability of (1) allowing access to only a single process for accessing the peripheral device and (2) the capability to provide access to a first process while simultaneously and concurrently providing access to a second process to a second port.