Abstract: A high frequency wafer probe for measuring characteristics of a device operating in a high frequency range includes a waveguide serving as a grounding conductor of the probe, an end of which is open, having a tip and extending from an upper wall of the waveguide in the vicinity of the open end which gradually increases in extent as it approaches the open end and the tip; a signal contact part disposed on a tip of the ridge for contacting a signal input terminal of a device under test; and a plurality of grounding contact parts disposed on the same plane as the signal contact part opposite to each other with the signal contact part between two of the signal contact parts for contacting a plurality of grounding terminals of a device under test. In this structure, the contact parts of the probe can be accurately positioned on the terminals of an IC chip under test, and the contact conditions are easily visually confirmed. In addition, a high frequency wafer probe with low loss and low reflection is achieved.
Abstract: A test fixture for testing circuit boards includes an array of test probes mounted to a probe plate and held in contact with test points in circuits printed on the board. The circuit array is indexed with respect to a fiducial mark on the board. The fiducial mark is sensed, and an optical reading shows the alignment or misalignment of the test points on the board relative to the probes. The top plate position is adjusted to move the board relative to the probes to correct misalignment. The optical reading indicates movement of the board to a corrected position necessary to align the test points to the probes. Board alignment can be optically sensed by a bore scope and an image enlarger and video probe that produce images of the fiducial mark and a known zero reference point on a video monitor. The zero reference is adjustable electronically during calibration.
Type:
Grant
Filed:
December 14, 1992
Date of Patent:
April 18, 1995
Assignee:
Everett Charles Technologies, Inc.
Inventors:
Mark A. Swart, Charles J. Johnston, David R. Van Loan
Abstract: A burn-in apparatus for use in burn-in tests includes a burn-in test chamber for accommodating a plurality of semiconductor devices to be tested. The burn-in apparatus further includes measuring means for detecting electric characteristics of temperature sensors built in semiconductor devices to measure junction temperatures of the semiconductor chips built in the semiconductor devices. Based on outputs of the measuring means, control means controls electric power feed amounts to the integrated circuits of the semiconductor chips and/or environmental temperatures in the burn-in test chambers. Thus, the junction temperatures are maintained in a set temperature range, and accuracy of screening tests can be improved.
Abstract: A semiconductor test chip for use in semiconductor fabrication fault analysis, comprises an n.times.m array of transmission gate cells arranged such that within a given row respective strips of conductive material of a first type form common source and drain electrodes for the transistors of the row, the sources and drains of each row being independent, and within a column strips of conductive material of a second type form common gate electrodes such that each column of transistors can be turned on independently. An input circuit permits a predetermined bit pattern to be selectively applied to the inputs of the rows of transmission gate cells. A demultiplexer including output transmission gates is connected to respective outputs of the rows of the array for selectively addressing the output of each row of transmission gate cells.