Patents Examined by B. D. Thomson
  • Patent number: 6970815
    Abstract: A method of discriminating between different types of simulated scan failures includes simulating a scan enable signal to a circuit represented by a netlist corresponding to a scan chain coupled to combinatorial logic being tested, simulating initiation of a data capture cycle in the netlist corresponding to the scan chain, the data capture cycle simulating a series of scan flops from the scan chain being simulated together with the combinatorial logic and simulating scanning data out from each flop in the scan chain and into a test program. The test program extracts the simulated scan flops and graphically displays the simulated scan flops versus time.
    Type: Grant
    Filed: November 18, 1999
    Date of Patent: November 29, 2005
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Jerome Bombal, Laurent Souef
  • Patent number: 6947882
    Abstract: A regionally time multiplexed emulation system includes an emulator for emulating a circuit design. The emulator includes a plurality of reconfigurable logic devices with buffered I/O pins and reconfigurable logic elements. The reconfigurable logic devices are reconfigurable to emulate a circuit design using at least one user clock to clock the logic elements and at least one signal routing clock to time multiplex the routing of emulation signals between the reconfigurable logic devices, with the at least one signal routing clock being independent of the at least one user clock.
    Type: Grant
    Filed: September 24, 1999
    Date of Patent: September 20, 2005
    Assignee: Mentor Graphics Corporation
    Inventors: Frederic Reblewski, Olivier Lepaps, Jean Barbier
  • Patent number: 6847988
    Abstract: In a service providing system, a plurality of information acquiring computers for acquiring informations are connected via a network to a plurality of information providing computers for providing information. A service providing computer for executing an information providing service with respect to apparatuses for acquiring information is interposed between a plurality of in information acquiring apparatuses and a plurality of information providing apparatuses. The service providing computer receives a content of a request of the information acquiring computer, and determines a sort of information to be provided with a user based upon a quality of this request content, individual information and past historical information of the user, and also various sorts of conditions when the request is received. The service providing computer requests at least one of these information providing computers to provide the information.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: January 25, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Junichi Toyouchi, Kinji Mori, Katsumi Kawano, Yoshinori Honda, Shigeki Hirasawa
  • Patent number: 6714903
    Abstract: A cell for inclusion in a cell library used in designing integrated circuits. The cell includes a signal processing circuit and a buffer circuit for buffering a signal external to an integrated circuit in which the cell is to be included. The cell also includes layout information for specifying a layout of an interconnecting trace between the signal processing circuit and the buffer circuit. The invention is also directed to a method for performing layout and routing during design of an integrated circuit, in which cells are obtained from a cell library, the obtained cells are laid out on an integrated circuit die, interconnections are routed between the cells.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: March 30, 2004
    Assignee: LSI Logic Corporation
    Inventors: Wei-Mun Chu, Sudhakar R. Gouravaram, Son Nguyen