Patents Examined by B. Everhart
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Patent number: 5470799Abstract: The present invention provides a method for removing a natural gas film or contaminant adhering on a surface of a silicon semiconductor substrate. The semiconductor substrate having the natural oxide film or contaminant adhered thereon is placed in a chamber. Then, a HCl gas is introduced into the chamber. The semiconductor substrate is heated at a temperature in the range of 200.degree..about.700.degree. C., while ultraviolet rays are irradiated into the chamber. According to the method, the reaction of the natural oxide with HCl gas is promoted by a synergistic effect of light and heat energy. Therefore, the natural oxide film or contaminant can be removed at a lower temperature with the help of the light energy.Type: GrantFiled: April 24, 1989Date of Patent: November 28, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiromi Itoh, Masanobu Iwasaki, Akira Tokui, Katsuhiro Tsukamoto
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Patent number: 5443997Abstract: A method for heating or cooling a semiconductor wafer in semiconductor processing apparatus is described which comprises directing into contact with a surface of the wafer at least a portion of one or more components of the process gas to transfer heat between the wafer and a wafer support positioned in the apparatus adjacent to the wafer. Method and apparatus are also described for controlling the total flow of process gas through the apparatus and for monitoring the pressure in said apparatus to maintain the desired pressure therein.Type: GrantFiled: May 13, 1992Date of Patent: August 22, 1995Inventors: Chiu-Wing Tsui, Richard H. Crockett
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Patent number: 5431772Abstract: A two step method of etching a silicon nitride layer carrying a surface oxygen film from a substrate in a plasma reactor employs the steps of (1) a breakthrough step of employing a plasma of oxygen free etchant gases to break through and to remove the surface oxygen containing film from the surface of the silicon nitride layer, and (2) a main step of etching the newly exposed silicon nitride with etchant gases having high selectivity with respect to the silicon oxide underlying the silicon nitride. The plasma etching can be performed while employing magnetic- enhancement of the etching. The plasma etching is performed in a plasma reactor comprising a low pressure, single wafer tool. Plasma etching is performed while employing magnetic-enhancement of the etching. The etchant gases include a halide such as a bromide and a fluoride in the breakthrough step. The etchant gases include an oxygen and bromine containing gas in the main step.Type: GrantFiled: October 19, 1992Date of Patent: July 11, 1995Assignee: International Business Machines CorporationInventors: Wayne T. Babie, Kenneth L. Devries, Bang C. Nguyen, Chau-Hwa J. Yang
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Patent number: 5426073Abstract: In wafer processes, after at least one layer which constitutes a structural member of a functional semiconductor element is formed on a semiconductor wafer, a brittle, excessive deposition on an edge of the semiconductor wafer is removed by grinding or etching of the wafer edge until the underlying wafer is exposed. The removal of the excessive deposition on the wafer edge reduces dust generation caused from crack and peel-off of the excessive deposition on the wafer edge, even if the wafer edge contacts a jig, and the like. Thus, the reduction in dust generation improves production yields of highly integrated semiconductor devices.Type: GrantFiled: October 13, 1993Date of Patent: June 20, 1995Assignee: Fujitsu LimitedInventors: Kazunori Imaoka, Yoichi Fujisawa
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Patent number: 5405489Abstract: The surface of a borophosphosilicate glass (BPSG) dielectric film is changed through a surface treatment, such as by plasma etching with N.sub.2 O, O.sub.3 or O.sub.2. Erosion caused by H.sub.2 SO.sub.4 boiling or by humidity absorption from the atmosphere is thereby reduced so that reflow processing at temperatures below 850.degree. C. is possible and an interlayer dielectric film of excellent planarity is thus formed.Type: GrantFiled: October 30, 1992Date of Patent: April 11, 1995Assignee: Samsung Electronics Co., Ltd.Inventors: Changgyu Kim, Changki Hong, Uin Chung, Yongchul Ahn
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Patent number: 5393710Abstract: A method is disclosed for manufacturing a very fast micro light valve of the type used to control the passage of light through a pixel. The method comprises preparing a substrate, which can be made of glass, and forming transparent electrodes on the main surface of the substrate. Next an insulating layer is deposited on the substrate and a first sacrificial layer is formed on the insulating layer. A pattern shifting element layer is formed on the first sacrificial layer and a second sacrificial layer is formed on the substrate and provided with a shifting element layer. After portions of the sacrificial layers are removed by etching to form a frame contact portion, a patterned frame layer is formed on the frame contact portion. Then a frame and a shifting element capable of moving in the frame under an applied external electrostatic force are formed by removing the remaining sacrificial layers.Type: GrantFiled: November 9, 1993Date of Patent: February 28, 1995Assignee: Electronics and Telecommunications Research InstituteInventors: Gyeong-Lyong Park, Sin-Chong Park, Hyung-Moo Park
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Patent number: 5380682Abstract: A wafer processing cluster tool, having one or more load-locks, is provided with one or more batch preheating modules that receive wafers only from the cluster tool transport module at the internal vacuum pressure of the machine. The loading, unloading, handling and processing of wafers in the machine can occur while other wafers are being preheated. The preheat module has a vertically moveable rack and is loaded with various sized batches of wafers with no vacant positions between them. Wafer shaped shields may occupy positions adjacent top and bottom wafers to cause them to heat the same as other wafers in the rack. Infrared lamps positioned outside of quartz windows heat wafers in the preheat module. The rack may rotate to improve heating uniformity. Temperature sensors, such as pyrometers, that do not contact the wafers being preheated, measure temperature for control of the heating of the lamps.Type: GrantFiled: November 3, 1993Date of Patent: January 10, 1995Assignee: Materials Research CorporationInventors: Richard C. Edwards, Michael S. Kolesa, Hiroichi Ishikawa
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Patent number: 5380683Abstract: Sapphire, a highly stable oxide of aluminum having the chemical formula of Al.sub.2 O.sub.3, is placed in a crucible. The crucible is heated to vaporize the sapphire therein. The sapphire vapor is ejected through a nozzle in the crucible and into a region having a vacuum pressure of approximately 10.sup.-5 Torr or less. As the vapor leaves the crucible through the nozzle, atom aggregates or clusters are formed through a supercooled phenomenon due to adiabatic expansion. The vacuum region has disposed therein a substrate of silicon. The sapphire vapor is accelerated towards the substrate where it deposits on a surface of the substrate in a uniformly distributed thin layer.Type: GrantFiled: October 2, 1992Date of Patent: January 10, 1995Assignee: United Technologies CorporationInventors: Scott M. Tyson, Richard Y. Kwor, Leonard L. Levenson
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Patent number: 5380398Abstract: A method for semiconductor device fabrication that uses a mixture of SiCl.sub.4, CF.sub.4, O.sub.2, and He to selectively etch GaAs with respect to AlGaAs. Etch selectivities greater than 300:1 are obtained.Type: GrantFiled: November 25, 1992Date of Patent: January 10, 1995Assignee: AT&T Bell LaboratoriesInventor: Lawrence E. Smith
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Patent number: 5374318Abstract: A low energy (10 to 300 eV), mass-selected ion beam is used to deposit thin films on atomically clean substrate surfaces. For example, a C.sup.+ ion beam may be used to deposit a chemically bonded diamond or diamondlike film on a substrate at room temperature. For thin carbon films, the initial monolayer of the deposited film is in the form of a carbide layer which is chemically bonded to the substrate atoms. The film evolves gradually over the next several layers deposited, through intermediate structures, into a diamond structure. The optimum C.sup.+ energy range for formation of the diamond structure is about 30 to 175 eV. Below 10 eV the final diamond structure has not been attained and above 180 eV there is a sharp increase in the dose required to attain this final structure. Multiple ion beams may be used to deposit multicomponent films including films doped with very low concentrations of foreign atoms. The diamond films produced by this process are found to be free of impurities, inert to O.sub.Type: GrantFiled: February 24, 1989Date of Patent: December 20, 1994Assignee: University of HoustonInventors: John W. Rabalais, Srinandan R. Kasi
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Patent number: 5368647Abstract: A photo-excited processing apparatus includes a reaction chamber to be filled with raw gas, light excitation means for irradiating a light beam through a light transmissive window formed in the reaction chamber to excite the raw gas, and cylindrical reflection means having a center axis passing through a center of light emission of the light source means and having a reflection plane on an inner surface thereof for directing a portion of the light beam emitted from the light source means to the light transmissive window.Type: GrantFiled: March 11, 1994Date of Patent: November 29, 1994Assignee: Canon Kabushiki KaishaInventor: Nobumasa Suzuki
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Patent number: 5366588Abstract: Method of manufacturing an electrically conductive pattern of tin-doped indium oxide (ITO) on a substrate.Tin-doped indium oxide (ITO) can be selectively etched relative to the metals Mo, W and TiW in an etching bath which is obtained by diluting concentrated halogen acid, for example hydrochloric acid, with a liquid having a lower dielectric constant than water, such as acetic acid or methanol. This is particularly advantageous in the manufacture of the MIM switching elements which are present on the active plate of LCDs.Type: GrantFiled: March 3, 1993Date of Patent: November 22, 1994Assignee: U.S. Philips CorporationInventors: Monica Scholten, Johannes E. A. M. Van Den Meerakker, Johannes W. M. Jacobs
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Patent number: 5354387Abstract: A composite BPSG insulating and planarizing layer is formed over stepped surfaces of a semiconductor wafer by a novel two step process. The composite BPSG layer is characterized by the absence of discernible voids and a surface which is resistant to loss of boron in a subsequent etching step. The two step deposition process comprises a first step to form a void-free BPSG layer by a CVD deposition using gaseous sources of phosphorus and boron dopants and tetraethylorthosilicate (TEOS) as the source of silicon; and then a second step to form a capping layer of BPSG by a plasma-assisted CVD deposition process while again using gaseous sources of phosphorus and boron dopants, and TEOS as the source of silicon, to provide a BPSG cap layer having a surface which is non-hygroscopic and resistant to loss of boron by subsequent etching.Type: GrantFiled: August 25, 1992Date of Patent: October 11, 1994Assignee: Applied Materials, Inc.Inventors: Peter W. Lee, David N. K. Wang, Makoto Nagashima, Kazuto Fukuma, Tetsuya Sato
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Patent number: 5354715Abstract: A high pressure, high throughout, single wafer semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature process for forming a highly conformal layer of silicon dioxide from a plasma of TEOS, oxygen and ozone is also disclosed. This layer can be planarized using an etchback process. Silicon oxide deposition and etchback can be carried out sequentially in the reactor.Type: GrantFiled: April 1, 1992Date of Patent: October 11, 1994Assignee: Applied Materials, Inc.Inventors: David N-K. Wang, John M. White, Kam S. Law, Cissy Leung, Salvador P. Umotoy, Kenneth S. Collins, John A. Adamik, Ilya Perlov, Dan Maydan
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Patent number: 5354386Abstract: A multi-step plasma etch method for etching a tapered via having uniform bottom diameter ("CD") and extending through the resist and into the oxide layer of a coated semiconductor substrate, and a coated semiconductor substrate whose coating has been plasma etched to define such a tapered via. The first step of the inventive method is an anisotropic oxide plasma etch operation, preferably employing a plasma consisting primarily of CF.sub.4, which produces a non-tapered via having diameter substantially equal to CD and extending through the resist and into the oxide layer. A preferred embodiment of the inventive method includes a second step defining an upper sloping via portion without significantly increasing the diameter of a lower portion of the non-tapered via. This second step is a tapered resist plasma etch operation employing a mixture of oxygen (O.sub.2) and CF.sub.4. The slope of the upper sloping via portion may be controlled by varying the ratio of oxygen to CF.sub.4.Type: GrantFiled: March 24, 1989Date of Patent: October 11, 1994Assignee: National Semiconductor CorporationInventors: David W. Cheung, Norman E. Abt, Peter A. McNally
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Patent number: 5354710Abstract: A method of manufacturing semiconductor devices comprises the steps of preparing a semiconductor substrate having a surface and a natural oxide film on the surface, forming an adsorption enhancement layer on the surface of the semiconductor substrate, forming an impurity adsorption layer containing impurities on the adsorption enhancement layer, and thermally diffusing the impurities through the adsorption enhancement layer and the natural oxide film into the substrate.Type: GrantFiled: February 12, 1993Date of Patent: October 11, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Hideichi Kawaguchi, Yoshitaka Tsunashima, Kikuo Yamabe, Katsuya Okumura
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Patent number: 5352248Abstract: A method of measuring and controlling the temperature of articles stacked in parallel in a chamber. A pyrometer is positioned outside of a chamber and directed, either directly or with mirrors, through a window in the chamber wall so that only energy from wafers removed from the ends of the stack is received by the pyrometer. The pyrometer is inclined at an angle so that substantially all energy from the opposite side of the stack and reflected through spaces between facing parallel pairs of wafer surfaces will have been reflected a large number of times by the wafers before entering the pyrometer. Thus, regardless of the emissivity or transmissivity of the wafers, the energy incident upon the pyrometer will approach that emitted by a black body of the same temperature as the wafers, and the temperature read by the pyrometer will be independent of the emissivity or transmissivity of the wafers.Type: GrantFiled: April 15, 1992Date of Patent: October 4, 1994Assignee: Materials Research CorporationInventors: Hiroichi Ishikawa, Michael S. Kolesa
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Patent number: 5352328Abstract: The onset of haze on silicon wafers is controlled by treating the wafers with a chemical selected from the group consisting of hot water and isopropyl alcohol and then storing the treated wafers in an inert atmosphere such as nitrogen or argon.Type: GrantFiled: December 15, 1992Date of Patent: October 4, 1994Assignee: AT&T Bell LaboratoriesInventors: Yaw S. Obeng, Edward J. Vajda
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Patent number: 5352636Abstract: A method is described for cleaning a silicon surface of a semiconductor wafer in a vacuum chamber while radiantly heating said silicon surface to maintain it within a first temperature range in the presence of hydrogen gas; then quickly cooling the wafer down to a second temperature range by reducing the radiant heat; and then forming a layer of either polysilicon or oxide over the cleaned surface within this second temperature range without removing the cleaned wafer from the chamber. By cleaning the wafer and then depositing polysilicon or growing oxide over the cleaned silicon surface in the same vacuum chamber, formation of oxides and other contaminants on the cleaned silicon surface between the cleaning step and the deposition or growth step is inhibited, resulting in a higher quality polysilicon or oxide layer formed over the cleaned silicon surface.Type: GrantFiled: January 16, 1992Date of Patent: October 4, 1994Assignee: Applied Materials, Inc.Inventor: Israel Beinglass
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Patent number: 5350492Abstract: A method is disclosed for removing oxide from the surface of a semiconductor body having a thick oxide and an adjoining nitride-covered thin oxide, without subjecting the surface to significant over-etching and thus avoiding degredation of the surface of the semiconductor body. The thick oxide is first etched for a period of time so that a portion of the thick oxide remains, and has a thickness comparable to that of the thin oxide. The nitride covering the thin oxide is next removed without appreciably etching either the remaining portion of the thick oxide or the thin oxide. Finally, the thin oxide and the remaining portion of the thick oxide are removed, without appreciably over-etching the surface of the semiconductor body.Type: GrantFiled: September 18, 1992Date of Patent: September 27, 1994Assignee: Advanced Micro Devices, Inc.Inventors: Steven C. Hall, Mark I. Gardner, Henry J. Fulford, Jr.