Abstract: A push-pull switching circuit including two grounded emitter transistors 5, 6 controlled by a pair of AND gates 3, 4. The collector output of each transistor is fed back to an input of the AND gate controlling the other transistor, the remaining AND gate inputs being supplied by the Q and Q outputs of a flip-flop circuit 2. During the prolonged conduction of each transistor due to minority carrier storage, its lowered collector potential prevents the enabled AND gate for the other transistor from raising its output and initiating conduction, thereby avoiding overlapping or simultaneous transistor conduction.