Abstract: A display device includes a planarization layer covering transistors in a display area on a substrate, an organic light emitting diode on the planarization layer, a pad electrode in a non-display area on the substrate surrounding the display area, and a sacrificial layer remnant capping a side surface of the pad electrode.

Abstract: In a method for manufacturing a semiconductor device, fin structures each having an upper portion and a lower portion, are formed. The lower portion is embedded in an isolation insulating layer disposed over a substrate and the upper portion protrudes the isolation insulating layer. A gate dielectric layer is formed over the upper portion of each of the fin structures. A conductive layer is formed over the gate dielectric layer. A cap layer is formed over the conductive layer. An ion implantation operation is performed on the fin structures with the cap layer. The ion implantation operation is performed multiple times using different implantation angles to introduce ions into one side surface of each of the fin structures.

Abstract: A flexible organic light-emitting display device may include: a first polymer layer; a first transparent conductive layer over the first polymer layer; a first inorganic layer over the first transparent conductive layer; and a plurality of pixels on the first inorganic layer and each including an organic light-emitting diode, and a driver configured to drive the organic light-emitting diode.

Abstract: A wafer expanding method for expanding a wafer having a plurality of rectangular devices respectively formed in a plurality of separate regions defined by a plurality of division lines, thereby increasing spacing between any adjacent ones of the devices, each rectangular device having a pair of shorter sides and a pair of longer sides. The wafer expanding method includes a jig preparing step of preparing an annular jig having an elliptical opening, the elliptical opening having a shorter portion for restricting a width of the annular exposed portion in a first direction where the shorter sides of the devices extend to a first width and a longer portion for restricting the width of the annular exposed portion in a second direction where the longer sides of the devices extend to a second width larger than the first width.

Abstract: Embodiments of the invention include a wafer having gate stacks over channel fins. The wafer includes a first channel fin in an n-type region of a substrate, a second channel fin in a p-type region of the substrate, and a gate dielectric over the substrate and the first and second channel fins. A work function metal stack is over the gate dielectric, the first channel fin in the n-type region, and the second channel fin in the p-type region. The work function metal stack over the gate dielectric and the first channel fin in the n-type region forms a first work function metal stack. The work function metal stack over the gate dielectric and the second fin in the p-type region forms a second work function metal stack. The first work function metal stack includes a shared layer of work function metal shared with the second work function metal stack.

Abstract: A wafer expanding method increases spacing between adjacent devices formed on a wafer. The method includes preparing an annular jig having a first restricting portion, a second restricting portion, and a curved restricting portion connecting the first restricting portion and the second restricting portion, mounting a ring frame supporting the wafer through an adhesive tape on a cylindrical frame fixing member, next mounting the annular jig on the ring frame, and next fixing the ring frame and the annular jig to the cylindrical frame fixing member, and operating a cylindrical pushing member having an outer circumference corresponding to an outer circumference of the wafer to push up an annular exposed portion of the adhesive tape defined between the wafer and the ring frame and thereby lift the wafer away from the ring frame, thereby expanding the annular exposed portion and increasing the spacing between the adjacent devices.

Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, the tunnel barrier layer is expressed by a composition formula of AB2Ox (0<x?4), and has a spinel structure in which cations are arranged in a disordered manner, the tunnel barrier layer has a lattice-matched portion and a lattice-mismatched portion, A is a divalent cation of plural non-magnetic elements, B is an aluminum ion, and in the composition formula, the number of the divalent cation is smaller than half the number of the aluminum ion.

Abstract: Provided are a laser annealing apparatus, a laser annealing method, and a mask with which scan nonuniformity can be decreased. According to the present invention, all or some openings of a plurality of openings are configured so that a partial subregion of a prescribed region is irradiated with laser light. The plurality of openings are configured so that, between prescribed regions irradiated with laser light via a group of openings in one row arranged in a row direction and prescribed regions irradiated with laser light via a group of openings in another row arranged in the row direction, the number of times of laser light radiations in subregions having the same occupying region is the same, and at least two openings of a group of openings arranged in a column direction have different positions or shapes.

Abstract: An organic light emitting diode (“OLED”) display device includes a substrate having a display region having a light emitting region and a peripheral region surrounding the light emitting region, a pad region at a first side of the display region, and a trench at a second side of the display region, a plurality of light emitting structures on the light emitting region of the substrate, an active pattern along a profile of the trench on the peripheral region of the substrate, the active pattern being adjacent to the trench and including a pattern protrusion, and an upper gate wiring on and overlapping the active pattern, the upper gate wiring having a wiring protrusion adjacent to the pattern protrusion.

Abstract: A transportation preparation operation for transporting a semiconductor wafer from a treatment chamber is started before a temperature of the semiconductor wafer decreases to a transportable temperature. A gate valve is closed after a treatment on the semiconductor wafer is started, and an operation of transporting the semiconductor wafer into the treatment chamber is completed. A period of time for treating the semiconductor wafer and a period of time for transporting the semiconductor wafer in and out are overlapped with each other, thus a time required for transporting the semiconductor wafer W into and out of the treatment chamber can be reduced.

Abstract: The number of masks and photolithography processes used in a manufacturing process of a semiconductor device are reduced. A first conductive film is formed over a substrate; a first insulating film is formed over the first conductive film; a semiconductor film is formed over the first insulating film; a semiconductor film including a channel region is formed by etching part of the semiconductor film; a second insulating film is formed over the semiconductor film; a mask is formed over the second insulating film; a first portion of the second insulating film that overlaps the semiconductor film and second portions of the first insulating film and the second insulating film that do not overlap the semiconductor film are removed with the use of the mask; the mask is removed; and a second conductive film electrically connected to the semiconductor film is formed over at least part of the second insulating film.

Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.

Abstract: The present disclosure provides a display device. The display device includes a first substrate, the first substrate being provided with a first relief groove, a second substrate, the second substrate being provided with a second relief groove, and a sealant. The sealant is sandwiched between the first substrate and the second substrate so as to seal the first substrate and the second substrate. Furthermore, the sealant is spaced apart from outer edges of the first substrate and the second substrate. The first relief groove is located between the sealant and the outer edge of the first substrate, and the second relief groove is located between the sealant and the outer edge of the second substrate.

Abstract: Embodiments of the invention are directed to a method that includes forming a first channel fin in an n-type region of a substrate, forming a second channel fin in a p-type region of the substrate, and depositing a gate dielectric over the substrate and the first and second channel fins. A work function metal stack is deposited over the gate dielectric, the first fin in the n-type region, and the second fin in the p-type region. The work function metal stack over the gate dielectric and the first fin in the n-type region forms a first work function metal stack. The work function metal stack over the gate dielectric and the second fin in the p-type region forms a second work function metal stack. The first work function metal stack includes at least one shared layer of work function metal that is shared with the second work function metal stack.

Abstract: An electro-optical panel includes: an electro-optical element emitting a light or adjusting a transmittance of a light; and a stretch film including a polymeric material, wherein a main stretching axis direction of the stretch film is disposed within a range of ±30° with respect to a side of the electro-optical panel.

Abstract: A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate. A second dielectric layer is disposed between the floating gate and the control gate, having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof. A third dielectric layer is disposed between the second dielectric layer and the control gate, and includes a dielectric material having a dielectric constant higher than silicon nitride.

Abstract: In accordance with an embodiment of the present invention, a memory cell is provided. The memory cell includes a first L-shaped bottom source/drain including a first dopant, and a first adjoining bottom source/drain region abutting the first L-shaped bottom source/drain, wherein the first adjoining bottom source/drain region includes a second dopant that is the opposite type from the first dopant.

Abstract: Optical control modules for integrated circuit device patterning and reticles and methods including the same. The methods include exposing, via a reticle, initial and subsequent reticle exposure fields on a surface of a semiconductor substrate. The initial and subsequent reticle exposure fields pattern corresponding array regions and margin regions on the semiconductor substrate. The initial and subsequent reticle exposure fields partially overlap such that an initial optical control module (OCM), which is patterned during exposure of the initial reticle exposure field, and a subsequent OCM, which is patterned during exposure of the subsequent reticle exposure field, both are positioned within a single control module die. The reticles include reticles that can be utilized during the methods or that can form the integrated circuit devices. The integrated circuit devices include integrated circuit devices formed utilizing the methods or the reticles.

Abstract: A III-nitride power handling device and the process of making the III-nitride power handling device are disclosed that use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity. An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of AlN and GaN. Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations. The disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.