Abstract: A method of fabricating a contact window of a semiconductor device, whereby a contact window of a semiconductor device is increased to offset any incline phenomenom and avoid unwanted increase in contact sheet resistance, comprises forming a lower conductive member on a semiconductor substrate, forming a first insulative film on the lower conductive member, the first insulative film being formed of an insulative material doped with impurities at a first level of concentration, the first insulative film having a wet etch rate that is proportional to the level of concentration of impurities, forming a second insulative film on the first insulative film, the second insulative film being formed of an insulative material doped with impurities at a second level of concentration that is lower than the first level of concentration of impurities, the second insulative film also having a wet etch rate that is proportional to the level of concentration of impurities, opening a contact window and exposing the lower condu

Abstract: A hydrogen barrier layer is formed above a ferroelectric thin film in an integrated circuit. The hydrogen barrier layer is directly over a protected segment of the ferroelectric thin film, while a sacrificial segment of the ferroelectric thin film extends laterally beyond the edges of the hydrogen barrier layer. The sacrificial segment absorbs hydrogen so that it cannot diffuse laterally into the protected segment of the ferroelectric thin film. After it absorbs hydrogen, the sacrificial segment is etched away to allow electrical connection to circuit layers below it. The ferroelectric thin film preferably comprises a layered superlattice compound. Excess bismuth or niobium added to the standard precursor solution of a strontium bismuth tantalum niobate compound helps to reduce hydrogen degradation of the ferroelectric properties.

Abstract: A method of fabricating a DRAM capacitor uses tungsten nitride in the process of forming a capacitor. The structure of the capacitor is simple and the process is easily executed. Furthermore, the invention provides a method of forming tungsten nitride, comprising a step of implanting nitrogen into a tungsten silicide layer and a step of executing a rapid thermal process under ammonia gas to form a tungsten nitride layer on the surface of the tungsten silicide layer. The method of fabricating a DRAM capacitor comprises forming the tungsten silicide layer after forming a part smaller than a bottom electrode of the capacitor from doped polysilicon and forming tungsten nitride on the surface of the tungsten nitride layer.

Abstract: The present invention provides a semiconductor device which includes trench-type element isolation which performs accurate alignment without deteriorating a device capability, and a method of manufacturing such a semiconductor device. Since a dummy gate electrode (14A) is formed in an edge proximity region of a trench (10A), a structure which does not create an etching remainder is realized. In addition, since a height difference is provided in a surface of the dummy gate electrode (14A) in such a manner that the height difference reflects a preliminary height difference between a surface of a silicon oxide films (2A) and a surface of a silicon substrate (1), it is possible to use the dummy gate electrode itself (14A) as an alignment mark.

Abstract: The invention provides a manufacturing method of forming a bottom plate for a capacitor on a substrate, wherein the substrate comprises a MOS transistor having a gate and a pair of source/drain regions. A crown-liked conductive plate is formed over an insulation oxide layer and a contact plug. The crown-liked conductive plate penetrates the insulation layer and the stop layer, wherein the bottom of the crown-like conductive plate is electrically connected to the contact plug. The crown-like conductive plate, served as the bottom plate for a DRAM capacitor, is composed of tungsten silicide or a combination of a tungsten nitride layer and a tungsten layer.

Abstract: A transistor and a method of making the same are provided. The transistor includes a substrate and a gate dielectric layer positioned on the substrate that has first and second sidewall spacers. A gate electrode is positioned on the gate dielectric layer between the first and second sidewall spacers. A semiconductor layer is positioned on the substrate and adjacent the gate dielectric layer. First and second source/drain regions are provided wherein each of the first and second source/drain regions has a first portion positioned in the semiconductor layer and a second portion positioned in the substrate. Processing of the gate dielectric layer and the sidewall spacers is integrated.

Abstract: An adherent hardmask structure and method of etching a bottom electrode in memory device capacitor structures that dispenses with the need for any adhesion promoter during the etching of the bottom electrode. By using silicon nitride as a hardmask 220, the processing is simplified and a more robust capacitor structure can be produced. Silicon nitride 220 has been shown to yield significantly enhanced adhesion to platinum 210, as compared to silicon oxide formed by any method. Since silicon nitride 220 is oxidation resistant, it advantageously resists any oxygen plasma that might be used in the etch chemistry. This etching process can be used during processing of high-k capacitor structures in DRAMs in the ≧256 Mbit generations.

Abstract: The method of the present invention for forming a capacitor on a semiconductor substrate includes the following steps. At first, a first oxide layer is formed over the substrate and a nitride layer is then formed over the oxide layer. A second oxide layer is then formed over the nitride layer and a first silicon layer is formed over the second oxide layer. Next, a node opening is defined in the first silicon layer, the second oxide layer, and the nitride layer, upon the first oxide layer. Sidewall structures are then formed on sidewalls of the node opening. A contact opening is then defined in the first oxide layer under the node opening. The contact opening is defined in the first oxide layer under a region uncovered by the sidewall structures. The sidewall structures and a portion of the nitride layer nearby the node opening are removed to form undercut structures under the second oxide layer.

Abstract: Nonvolatile memory capable of programming and erasure and method for fabricating the same, the method comprising the steps of (1) forming an oxide film on a first conduction type semiconductor substrate, (2) conducting an annealing in an NO or N2O ambient to convert the oxide film into a vertical lamination of a first silicon oxynitride region containing nitrogen and a second silicon oxynitride region containing relatively less nitrogen compared to the first silicon oxynitride region formed on the substrate, (3) patterning a gate electrode on the second oxynitride region, (4) forming second conduction type source, and drain impurity diffusion regions in surfaces of the substrate on both sides of the gate electrode, whereby facilitating a simple and easy fabrication process, a low programming voltage, a high performance, and a high device reliability.