Abstract: An SOI high-voltage switch with an FET structure, in which a drift zone of one conductivity type is provided between a gate electrode and a drain electrode in the drain region. Pillar-like trenches in the form of a grid are incorporated in the drift zone and are filled with semiconductor material of the other conductivity type.

Abstract: A semiconductor layer is co-doped with two dopants. The first dopant is to generate charge carriers in the semiconductor material, and the second dopant is to promote atomic disorder within the material. When the semiconductor material is annealed, the second dopant becomes mobile and moves through the lattice so as to promote atomic disorder. This eliminates unwanted effects such as, for example, a reduction in the forbidden bandgap that can otherwise arise as a result of atomic ordering. The amount of diffusion of the second dopant during the annealing can be increased by making the initial concentration of the second dopant non-uniform over the volume of the semiconductor material.

Abstract: The present invention provides polymeric materials that can be used as a moisture/ion barrier layer for inhibiting the penetration of moisture and/or ions for coming into contact with the metal wiring found in chip level interconnects. The present invention also provides a means to protect the chip backside from being contaminated by metal atoms or metal ions which are capable of forming mobile silicides, which can migrate to the active sites of the semiconductor and destroy them. The present invention further provides methods of forming such polymeric barrier layers on at least one surface of an interconnect structure.

Abstract: This method forms an SRAM device with an array of cells having low resistance conductors for the reference potential (Vss) circuits connected to transistors in the SRAM device. First form an SRAM device with two pull-up transistors, two pull-down transistors and two pass gate transistors, including thin film gate electrode conductors and interconnection lines, each of the transistors having a drain region and a source region with source regions of the two pull-up transistors connected to a power supply voltage (Vcc). Then form a plurality of dielectric and metallization layers over the transistors, the conductors and the interconnection lines. Form a stack of layers over the transistors, the stack of layers comprising a plurality of metallization layers sandwiched between a plurality of dielectric layers. Form a conductive reference potential node electrically connected to the source region of each of the pull-down transistors.

Abstract: A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region of the FET includes a buried and confined metal plate for controlling short channel effects without significantly increasing junction capacitance.

Abstract: A semiconductor device and a fabrication method therefor improve electrostatic discharge (ESD) protecting property of an ESD protecting device in a fabrication method of a semiconductor device using a self-aligned silicide CMOS process. The semiconductor device has a silicide blocking portion which prevents a self-aligned silicified reaction by forming a gate electrode on drain and/or source of an ESD protecting device and simultaneously forming a dummy gate electrode which is separated from the gate electrode.