Abstract: An alignment logic circuit transferring segments of data from a first storage device to a second storage device is provided. The alignment logic circuit includes a first and second alignment stages, and an alignment control logic that controls the first and second alignment stages such that the first alignment stage outputs data aligned in a first dimension according to a second configuration, and the second alignment stage outputs data aligned in a second dimension according to the second configuration.A computer system with a DMA controller with a Memory Write and Invalidate logic circuit is provided. The Memory Write and Invalidate logic circuit generates a Memory Write and Invalidate enable signal when the DMA byte count is greater than or equal to a cacheline size, and the current transfer adders is a multiple of the cacheline size.

Abstract: A network management device for managing a plurality of network elements has a network element management data acquisition unit for acquiring, in stages, various management data possessed by the network elements when a session with a network element is resumed and when the network management device itself is started up, a rule management table for storing a dependence relationship between an operation and management data necessary to execute the operation, a feasible operation decision processing unit which, when an operation has been specified, refers to the dependence relationship to determine whether management data necessary to execute the operation has been acquired. If the necessary management data has been acquired, a network management execution unit executes network management conforming to the operation.

Abstract: A system and method for controlling the execution rate of an instruction processor on an instruction-by-instruction basis in a data processing system. The user controls the execution rate by specifying "cycle-slip" data for each instruction type in the instruction set. This cycle-slip data is used to force the instruction processor to idle for the specified number of execution cycles during the execution of the associated instruction type, thereby slowing down the rate of execution. Allowing rate control data to be unique for each instruction type allows temporary fixes to be implemented when timing-related hardware problems are discovered during system test. If desired, a uniform number of cycle slips can be imposed on all instructions so that the overall rate of the instruction processor is tailored to match the execution rate of slower peripheral devices.

Abstract: A data transfer system and method for copying an operating system from an original hard drive to a replacement hard drive such that the replacement hard drive can be substituted for the original hard drive in a self-initializing manner. The system includes a data transfer program that identifies the operating system on the original hard drive. The data transfer program prepares the operating system for copying to the replacement hard drive and then copies the operating system, including all files of the operating system, to the replacement hard drive. After the operating system is copied onto the replacement hard drive, the replacement hard drive can be substituted for the original drive, and the replacement hard drive will be operable in a self-initializing manner.

Abstract: In a synchronous arbitration unit with round-robin priority for arbitrating between N requests (Ri) for access to common resources of a multiprocessor system, the requests stored in an input register timed by a clock signal are applied as inputs to a fixed-priority arbitration network having 2N-1 inputs, N-1 of the requests being applied both to a first set of N-1 lower-priority inputs of the network and, through masking circuits which selectively mask the requests with a binary masking configuration generated by mask-generating circuits in accordance with predetermined priority-rotation criteria, to a second set of N-1 higher-priority inputs of the network, in the same order of input priority. The grant signals output by the network are latched in an output register after logical OR of the grant signals associated with the same request and the arbitration unit thus formed has a minimal arbitration time and is constituted by a small number of logic components.