Abstract: A postage meter control system includes a microcomputer having a programmable microprocessor. The microcomputer is in communication with a decoder integrated circuit (Decoder IC). The Decoder IC has a first write control flip-flop and a second write control flip-flop, as in the preferred embodiment there are redundant non-volatile memories. Each control flip-flop has an output to a respective AND gate. The Decoder IC includes a dual timer which has an output to the control flip-flops. As a result, when the microcomputer enters write routine, the timer releases the control flip-flops to allow the system to be write enabled. If the write routine encounters a error, resulting in the timer timing out, the timer resets the control flip-flop and communicates with the microcomputer to try a retry. A more detailed description, and other features and advantages will become apparent in conjunction with the detailed description of the preferred embodiment.

Abstract: An apparatus for and method of performing automatic test pattern generation for a digital circuit specified registers when the process of automatic test pattern generation for one or more faults is aborted which allow detection of circuit faults by scanning the specified registers. The scan request count of the specified registers is updated, and registers having a scan request count greater than the scan request count limit are recognized as critical registers. Automatic test pattern generation is performed while regarding the critical registers as scan registers.