Abstract: A self-adaptive hybrid cache and method of caching data objects. A set of cacheable data objects is partitioned among a set of cooperating caches (e.g., a cache cluster). A hybrid cache is configured to cache data objects that it owns (i.e., objects in its partition) as primary content and to also cache data objects that are owned by other caches as secondary content (e.g., based on demand for such objects). A hybrid cache stores and/or removes objects based on criteria such as validity, popularity, size, age, cost of replacing, amount of available cache space, whether the objects are primary or secondary, etc. Over time, the amount or ratio of primary and secondary data that a hybrid cache stores may fluctuate dynamically.

Abstract: The invention relates to host caching in data storage systems. In an embodiment, the invention provides a first host and a second host, each having memory. The host memory includes nonvolatile and volatile portions available for cache. Each host logically owns its volatile memory and the other host's nonvolatile memory. By assigning ownership in this way data can be transmitted between the hosts with little communication overhead. In addition, if the first host fails between write acknowledgment and destaging the write data, the write data is safely stored in the second nonvolatile memory of the second host. Thus, the second host can destage the data from the second nonvolatile memory. In addition, the host cache writes and reads the data rapidly by its nature.

Abstract: According to the present invention a cache within a multiprocessor system is speculatively filled. To speculatively fill a designated cache, the present invention first determines an address which identifies information located in a main memory. The address may also identify one or more other versions of the information located in one or more caches. The process of filling the designated cache with the information is started by locating the information in the main memory and locating other versions of the information identified by the address in the caches. The validity of the information located in the main memory is determined after locating the other versions of the information. The process of filling the designated cache with the information located in the main memory is initiated before determining the validity of the information located in main memory. Thus, the memory reference is speculative.

Abstract: A BIST controller (112) and methodology uses the DRAM controller (108) refresh signals to test the data retention characteristics of a DRAM memory array (132). The BIST controller blocks a fraction of the refresh cycles generated by the DRAM controller to provide a margin of confidence above the DRAM's specified retention time. The BIST controller is especially suited to embedded applications in which access to the memory is indirect and to applications in which the memory system is modular. The invention may also be used to characterize the actual retention time of a particular DRAM allowing the system to optimize the DRAM's refresh interval.

Abstract: A computer-implemented method and apparatus for transferring the contents of a general register, in a register stack, to a location in a backing store in a main memory are described. When transferring the contents of a general register to a location in the backing store, the invention proposes collecting attribute bits included in each general register of a predetermined group of registers in a temporary collection register. Once the temporary collection register has been filled, the contents of this register are written to the next available location in the backing store. Similarly, on the restoration of registers from the backing store, a collection of attribute bits saved in the backing register is transferred to a temporary collection register. Thereafter, each attribute bit is saved together with associated data into a general register, thereby to restore the former contents of each general register.

Abstract: A computer system processes system management interrupt (SMI) requests from plural system management (SM) requesters. Different SM requesters are provided with different priority levels such that high priority system management interrupts can be serviced without waiting for lower priority system management interrupts to be serviced completely. In particular, the system executes a first SMI handler routine in response to receiving a first SMI from a first SM requester. In response to receiving a second SMI asserted by a second SM requester, the system determines whether the second SMI request has been assigned a higher priority than the first SMI request. If so, then the system interrupts executing the first SMI handler routine and executes a second SMI handler routine corresponding to the second SMI request. Otherwise, the system completes executing the first SMI handler routine and then executes the second SMI handler routine.

Abstract: Methods and apparatus which enable threads to lock and to unlock objects disclosed. According to one aspect of the present invention, a method for associating an object with a first thread includes obtaining the contents of the object header field of the object. The contents obtained from the object header field are then stored into a first location within a stack which is associated with the first thread. A reference indicator, which identifies the stack in which the contents obtained from the object header field are stored, is then stored in the object header field. In one embodiment, the method further includes updating a status indicator associated with the object to essentially show that the reference indicator is stored in the object header field. In such an embodiment, the contents of the object header may include a header value, and the status indicator may be updated to indicate that the object is accessible to the first thread.

Abstract: Methods and apparatus for resolving access patterns in a data processing system using the pigeon hole principle are disclosed herein. The data processing system has a directed graph G of access patterns including a vertices set V representing cache items. Each cache item v has an access pattern defined by a path of vertices (v.sub.1 .fwdarw. , . . . , .fwdarw.v.sub.n), v.sub.1 representing the start of the path and v.sub.n representing the end of the path at cache item v. The method includes defining a prefix cache for directed graph G which contains a map between an access pattern (v.sub.1 .fwdarw. , . . . , .fwdarw.v.sub.k) and vertex v.sub.k for a kth level L in graph G, storing the prefix cache in a memory and, for a given access pattern (v.sub.1 .fwdarw. , . . . , .fwdarw.v.sub.n), searching the prefix cache for a prefix (v.sub.1 .fwdarw. , . . . , .fwdarw.v.sub.k) of the given access pattern that reaches the kth level L. If the search is successful, the method includes outputting vertex v.sub.

Abstract: An apparatus for and method of enhancing the performance of a multi-port internal cached DRAM (AMPIC DRAM) by providing an internal method of data validation within the AMPIC memories themselves to guarantee that only valid requested data is returned from them, or properly marked invalid data. A modified technique for identifying bad data that has been read out of AMPIC memory devices in the system.

Abstract: The invention provides a read-only memory and a latching circuit wherein data held in a first memory location is used to address the next memory location, in addition to providing a synchronous portion of the code. Accordingly, the data at the next memory address is used as a succeeding address and a subsequent portion of the code. The data is organized to repeat when the data stored in the address location is equal to the starting address.

Abstract: A region comprising a plurality of real pages in a part of a real storage unit is provided with a first key storage unit having a plurality of key storage entries each corresponding to one of the plurality of real pages, while a second region comprising a plurality of real pages in the second part of the real storage unit is provided with a second key storage unit having a single key storage entry. When a real address designated by an instruction to be executed belongs to the first region, an entry corresponding to this address is accessed by a storage protection control circuit. When this address belongs to the second region, the second key storage unit is accessed irrespective of the address. Further, a key within the accessed key information is compared with a key on a program status word (PSW) allocated to a program to determine whether the execution of the instruction is permitted.

Abstract: An instruction fetching device includes one or both of a cache device and a branch history table. The cache device stores a plurality of pairs, each pair including an instruction string divided into minimum unit instructions and an address of the instruction string. At the time of reading an instruction, an instruction string is selected and output by every minimum unit instruction from at least two pairs. The branch history table stores a plurality of pairs, each pair including a branch destination address and a set of an address of a branch instruction and a value obtained by subtracting a given value from the address.

Abstract: A cache memory structure comprises a cache memory that has a plurality of ports for reading data from the cache memory and a plurality of ports for writing data into the cache memory. A switching network matrix having controllable switch elements for connecting of the cache memory ports to bus terminals is arranged between the bus terminals and processors, to an instruction unit of a processor, to a main memory, and to the cache memory. The switch elements of the switching network matrix are controlled by a cache memory controller such that the bus terminals can be selectively connected to the write or read ports of the cache memory. With the assistance of the switching network matrix, it becomes possible to select the number of ports of the cache memory to be less than the plurality of bus terminals that access the cache memory.

Abstract: A hierarchical cache memory includes a high-speed primary cache memory and a lower speed secondary cache memory of greater storage capacity than the primary cache memory. To manage a huge number of data lines interconnecting the primary and secondary cache memories, the hierarchical cache memory is integrated on a plurality of integrated circuits which include all of the interconnecting data lines. Each integrated circuit includes a primary memory and a secondary memory for storing and retrieving data transferred over a first data input line and a first data output line that link the primary memory to a central processing unit. At any given time, a multi-bit word is addressed in the secondary memory, and a corresponding multi-bit word is addressed in the primary memory.

Abstract: A multiprocessor system having global data replicated in all local memories, each local memory related to one of the system central processing units (CPUs), where consistency of the global data in each of the local memories is provided by a global write procedure according to which an agent CPUZ, willing to modify a global data in its own local memory, issues a write command on the system bus for performing the write operation in the local memory of another destination CPU of the system and characterizes the write command as a global write, so that all the CPUs connected to the system bus (including CPUZ) detect such command, perform such write operation in their related local memory and provide the destination CPU with a signal indicative of a performed write operation, so that the destination CPU, as "replier", may signal to CPUZ the successful execution of the global write.