Abstract: According to one embodiment, a bearing surface of the head slider includes a leading step at the inflow end portion, a skirt portion at the inflow end portion, a leading pad on the leading step and including a junction extending to the skirt portion, first groove surfaces individually on the opposite sides of the junction and being continuous with a downstream central portion of the skirt portion, second groove surfaces on an upstream side of the first groove surfaces and formed deeper than the first groove surfaces, and negative-pressure grooves individually on the transversely opposite sides of the first groove surfaces between the second groove surfaces and the skirt portion and formed deeper than the second groove surfaces.

Abstract: A technique for efficiently handling write operation failures in a memory device which communicates with an external host device allows a page of data to be re-written to a memory array from a page buffer. The host provides user data, a first write address and a write command to the memory device. If the write attempt fails, the host provides a re-write command with a new address, without re-sending the user data to the memory device. Additional data can be received at a data cache of the memory device while a re-write from the page buffer is in progress. The re-written data may be obtained in a copy operation in which the data is read out to the host, modified and written back to the memory device. Additional data can be input to the memory device during the copy operation. Page buffer data can also be modified in place.

Abstract: An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.

Abstract: A novel system, computer readable storage medium and method for creating re-usable queries over complex data including hierarchies, trees and graphs is described. This is achieved by an object-oriented query language, where a class is a logical property of a data item, and inheritance is implication between such properties. Virtual method calls execute all relevant method implementations in most specific classes. Expressions can be multi-valued, thus avoiding the need for naming intermediate results. All constructs closely follow the syntax of mainstream object-oriented languages like Java.

Abstract: Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.

Abstract: In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states is then first programmed. Following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states.

Abstract: A memory according to an embodiment includes bit lines, word lines, source lines, magnetic tunnel junction elements and transistors that are serially connected between the bit lines and the source lines, respectively, and a sense amplifier that detects data stored in the magnetic tunnel junction elements. The semiconductor storage device includes multiplexers between the bit lines and the sense amplifier in order to select one of the bit lines to be connected to the sense amplifier, and write amplifiers that are located corresponding to memory cell blocks each of which includes memory cells each including the magnetic tunnel junction element and the transistor and are connected to the bit lines or connected via the multiplexers to the bit lines. To write data, the sense amplifier applies a write voltage to the bit lines and then the write amplifiers hold the write voltage.

Abstract: Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core, and a cache including a cache instruction port, a cache data port, and a port utilization circuitry configured to selectively fetch instructions through the cache instruction port and selectively pre-fetch instructions through the cache data port. Other embodiments are also described and claimed.

Abstract: A non-volatile storage system stores data by programming the data as binary data into blocks that have not yet been programmed with multi-state data and have not yet been programmed with binary data X times. The system transfers data from multiple blocks (source blocks) of binary data to one block (target block) of multi-state data using a multi-state programming process, where the target block has been previously programmed with binary data X times (or less than X times).

Abstract: According to one embodiment, a semiconductor device includes a first voltage generator, a second voltage generator, a first MOS transistor, and a controller. The first voltage generator outputs a first voltage to a first node. The second voltage generator outputs a second voltage to a second node. The first MOS transistor is capable of short-circuiting the first node and second node. The controller performs a control operation to short-circuit the first node and second node by turning on the first MOS transistor. The controller controls a period in which the first MOS transistor is kept in an on state based on time.

Abstract: A process is performed periodically or in response to an error in order to dynamically and adaptively optimize read compare levels based on memory cell threshold voltage distribution. One embodiment of the process includes determining threshold voltage distribution data for a population of non-volatile storage elements, smoothing the threshold voltage distribution data using a weighting function to create an interim set of data, determining a derivative of the interim set of data, and identifying and storing negative to positive zero crossings of the derivative as read compare points.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific value of the IC. The input regulator is operative to provide a regulated input to the IC during operation, such that the IC performance satisfies performance requirement.

Abstract: A time-shift image distribution system includes an image server and a time-shift image requesting apparatus. The image server includes a first communication unit configured to carry out communications with the time-shift image requesting apparatus, an image database configured to store image data of captured images in association with meta information for image data of a captured image matching search-condition information, and an image providing unit configured to provide the image data of the captured image detected by the searching unit to the time-shift image requesting apparatus. The time-shift image requesting apparatus includes a second communication unit configured to carry out communications with the image server, and a unit configured to send a search request including information representing an imaging time and information for identifying a subject image as search-condition information to the image server via the second communication unit.

Abstract: Exemplary embodiments relate to methods, systems, and storage mediums for managing content storage and selection activities. The method includes aggregating content from content providers and presenting the content to a content device. The method also includes monitoring consumption of storage space with respect to storage capacity in the content device, relocating content contained in the storage space of the content device when a predetermined condition is met, and providing access to relocated content. The relocation is operable for freeing up the storage space of the content device.

Abstract: A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.