Patents Examined by Belur Keshaven
  • Patent number: 6284646
    Abstract: A method for forming a metal layer for an integrated circuit device includes forming a first conductive layer on an integrated circuit substrate. While forming the first conductive layer, a reflection index of the first conductive layer is monitored, and the formation of the first conductive layer is terminated when the reflection index of the first conductive layer reaches a predetermined value. More particularly, the first conductive layer can be an aluminum layer having a thickness in the range of approximately 500 Angstroms to 1500 Angstroms.
    Type: Grant
    Filed: August 19, 1998
    Date of Patent: September 4, 2001
    Assignee: Samsung Electronics Co., Ltd
    Inventor: Hyeun-Seog Leem
  • Patent number: 6121128
    Abstract: A semiconductor structure and method of making the same are disclosed which includes a DRAM cell which has a transistor which includes a gate. The gate includes an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further has a single crystal semiconductor substrate having a source/drain region. An active conducting wordline is deposited on top of and electrically contacting a segment gate conductor, the wordline being a conductive material having a top and sidewalls. Electrically insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. The insulating material surrounding the active wordline includes silicon nitride overlying the top and surrounding a portion of the sidewalls thereof, and silicon dioxide surrounds the remainder of the side walls of the active wordline.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: September 19, 2000
    Assignee: International Business Machines Corporation
    Inventors: Mark C. Hakey, Steven J. Holmes, David V. Horak, Wendell P. Noble, Jr.