Abstract: The present invention provides a method of fabricating capacitor dielectric layer. A bottom electrode covered by a native oxide layer on a chip is provided. The chip is disposed into a low pressure furnace. A mixture of dichlorosilane and ammonia is introduced into the low pressure furnace to form a nitride layer on the native oxide layer. In the same low pressure furnace, nitrogen monoxide or nitric oxygen is infused to form an oxynitride layer on the nitride layer.

Abstract: A hybrid integrated circuit includes a metal lead frame, a wiring structure, an integrated circuit chip, and a lead. The wiring structure is comprised of a wiring layer formed on the upper surface of the lead frame through an insulating layer. The integrated circuit chip is arranged on the wiring structure and connected to a predetermined portion of the wiring structure. A terminal is arranged near the lead frame to be insulated and isolated from the lead frame and connected to the predetermined portion of the wiring structure. The insulating layer has an extending connecting portion extending from the wiring structure to be connected to the lead frame. A fixed potential is connected to the integrated circuit chip through the extending connecting portion and the lead frame.

Abstract: A process for fabricating a capacitor in a microcircuit, and the capacitor so fabricated. A first layer of a polycrystalline semiconductor, preferably polysilicon, is deposited. A layer of a binary metallic conductor, preferably tungsten silicide, is deposited on the first layer of polycrystalline semiconductor, and is annealed in an oxidizing atmosphere to produce an oxide layer that serves as the dielectric of the capacitor. A second layer of a polycrystalline semiconductor, also preferably polysilicon, is deposited on the oxide layer. The physical properties (index of refraction, charge to breakdown, breakdown voltage) of the dielectric so created are superior to those of the prior art dielectrics.

Abstract: This invention relates to a method of forming a landing pad on a semiconductor wafer comprising a silicon substrate, a dielectric layer, a passivation layer and a photo-resist layer. The photo-resist layer comprises a hole penetrating to the surface of the passivation layer which defines the position of the landing pad. An anisotropic etching through the hole is performed to vertically remove the passivation layer and a predetermined thickness of the dielectric layer under the hole to form a recess, and then the photo-resist layer is removed. A filling layer is deposited on the passivation layer and the recess. An etch-back process is performed to remove the filling layer on the bottom portion of the recess and form a circular spacer on the surrounding portion of the recess. Another anisotropic etching is performed to vertically remove the dielectric layer under the recess and down to the surface of the silicon substrate which forms a plug hole, over which the circular spacer is used as a hard mask.