Abstract: Techniques and mechanisms for controlling execution of an instruction sequence in a data stream processing engine. In an embodiment, a control unit of the data stream processing engine detects that execution of a first instruction in an instruction sequence has ended. In another embodiment, the control unit determines information regarding a next instruction of the instruction sequence which is to be executed. Control signals may be sent from the control unit to form a data path set for execution of the next instruction in the instruction sequence.

Abstract: A method and apparatus for register packing prior to register renaming in a microprocessor are provided. The method includes: receiving a plurality of micro operations (micro-ops) decoded from one or more instructions; packing a plurality of registers which are included in the micro-ops into a packed register structure including a plurality of packed registers based on a preset number of rename ports of a renamer through which the packed registers are read or written for register renaming; and sending the packed registers for register renaming.

Abstract: Embodiments of the invention relate to a computer system for storing an internal instruction loop in a loop buffer. The computer system includes a loop buffer and a processor. The computer system is configured to perform a method including fetching instructions from memory to generate an internal instruction to be executed, detecting a beginning of a first instruction loop in the instructions, determining that a first internal instruction loop corresponding to the first instruction loop is not stored in the loop buffer, fetching the first instruction loop, optimizing one or more instructions corresponding to the first instruction loop to generate a first optimized internal instruction loop, and storing the first optimized internal instruction loop in the loop buffer based on the determination that the first internal instruction loop is not stored in the loop buffer.

Abstract: A method for performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching. The method includes receiving a first instruction of an instruction sequence and a second instruction of the instruction sequence and determining if the first instruction and the second instruction can be optimized. In response to the determining that the first instruction and second instruction can be optimized, the method includes, preforming a pre-decode optimization on the instruction sequence and generating a new second instruction, wherein the new second instruction is not dependent on a target operand of the first instruction and storing a pre-decoded first instruction and a pre-decoded new second instruction in an instruction cache. In response to determining that the first instruction and second instruction can not be optimized, the method includes, storing the pre-decoded first instruction and a pre-decoded second instruction in the instruction cache.

Abstract: Event counter checkpointing and restoring is disclosed. In one implementation, a processor includes a first event counter to count events that occur during execution within the processor, event counter checkpoint logic, communicably coupled with the first event counter, to store, prior to a transactional execution of the processor, a value of the first event counter, a second event counter to count events prior to and during the transactional execution, wherein the second event counter is to increment without resetting after the transactional execution is aborted, event count restore logic to restore the first event counter to the stored value after the transactional execution is aborted, and tuning logic to determine, in response to aborting of the transactional execution, a number of the events that occurred during the transactional execution based on the stored value of the first event counter and a value of the second event counter.

Abstract: A system and method for executing a transaction in a transactional memory system is disclosed. The system includes a processor of a plurality of processors coupled to shared memory, wherein the processor is configured to execute a section of code, including a plurality of memory access operations to the shared memory, as an atomic transaction relative to the execution of the plurality of processors. According to embodiments, the processor is configured to determine whether the memory access operations include any of a set of disallowed instructions, wherein the set includes one or more instructions that operate differently in a virtualized computing environment than in a native computing environment. If any of the memory access operations are ones of the disallowed instructions, then the processor aborts the transaction.

Abstract: A return stack buffer (RSB) is modified such that each entry comprises two or more address slots. When a function is called, the address following the function call is pushed to the RSB and stored in a selected one of the address slots in a top entry in the RSB. One or more pointer bits within the entry are set to indicate which slot the address was stored in.

Abstract: A system for controlling, by a hypervisor, access to physical resources during execution of a virtual machine includes a physical disk and a hypervisor. The physical disk is provided by a computing device and stores at least a portion of a virtual disk. The hypervisor executes on the computing device. The hypervisor allocates, to the virtual disk, an amount of access to the physical disk. The hypervisor determines that a level of utilization of the physical disk has exceeded a threshold. The hypervisor limits, in response to the determination, access by the virtual disk to the physical disk.

Abstract: Augmented processor hardware contains a microcode interpreter. When encrypted microcode is included in a challenge from a service requiring authentication, the microcode may be passed to the microcode interpreter. Based on decryption and execution of the microcode taking place at the processor hardware, tampering by potentially abusive device software may be avoided.

Abstract: A method for performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching. The method includes receiving a first instruction of an instruction sequence and a second instruction of the instruction sequence and determining if the first instruction and the second instruction can be optimized. In response to the determining that the first instruction and second instruction can be optimized, the method includes, preforming a pre-decode optimization on the instruction sequence and generating a new second instruction, wherein the new second instruction is not dependent on a target operand of the first instruction and storing a pre-decoded first instruction and a pre-decoded new second instruction in an instruction cache. In response to determining that the first instruction and second instruction can not be optimized, the method includes, storing the pre-decoded first instruction and a pre-decoded second instruction in the instruction cache.

Abstract: The speed of task scheduling by a multitask OS is increased. A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided with a processing register and an execution control circuit operative to load data from a memory into a processing register and execute a task in accordance with the data in the processing register. The save circuit is provided with a plurality of save registers respectively associated with a plurality of tasks. In executing a predetermined system call, the execution control circuit notifies the task control circuit as such. The task control circuit switches between tasks for execution upon receipt of the system call signal, by saving, in the save register associated with a task being executed, the data in the processing register, selecting a task to be executed next, and loading data in the save register associated with the selected task into the processing register.

Abstract: An apparatus and method for generating a very long instruction word (VLIW) command that supports predicated execution, and a VLIW processor and method for processing a VLIW are provided herein. The VLIW command includes an instruction bundle formed of a plurality of instructions to be executed in parallel and a single value indicating predicated execution, and is generated using the apparatus and method for generating a VLIW command. The VLIW processor decodes the instruction bundle and executes the instructions, which are included in the decoded instruction bundle, in parallel, according to the value indicating predicated execution.

Abstract: Method, system, and computer program product for randomizing entropy on a parallel computing system using network arithmetic logic units (ALUs). In one embodiment, network ALUs on nodes of the parallel computing system pseudorandomly modify entropy data during broadcast operations through application of arithmetic and/or logic operations. That is, each compute node's ALU may modify the entropy data during broadcasts, thereby mixing, and thus improving, the entropy data with every hop of entropy data packets from one node to another. At each compute node, the respective ALUs may further deposit modified entropy data in, e.g., local entropy pools such that software running on the compute nodes and needing entropy data may fetch it from the entropy pools. In some embodiments, entropy data may be broadcast via dedicated packets or included in unused portions of existing broadcast packets.

Abstract: Method, system, and computer program product for randomizing entropy on a parallel computing system using network arithmetic logic units (ALUs). In one embodiment, network ALUs on nodes of the parallel computing system pseudorandomly modify entropy data during broadcast operations through application of arithmetic and/or logic operations. That is, each compute node's ALU may modify the entropy data during broadcasts, thereby mixing, and thus improving, the entropy data with every hop of entropy data packets from one node to another. At each compute node, the respective ALUs may further deposit modified entropy data in, e.g., local entropy pools such that software running on the compute nodes and needing entropy data may fetch it from the entropy pools. In some embodiments, entropy data may be broadcast via dedicated packets or included in unused portions of existing broadcast packets.

Abstract: Embodiments of the invention relate to a computer system for storing an internal instruction loop in a loop buffer. The computer system includes a loop buffer and a processor. The computer system is configured to perform a method including fetching instructions from memory to generate an internal instruction to be executed, detecting a beginning of a first instruction loop in the instructions, determining that a first internal instruction loop corresponding to the first instruction loop is not stored in the loop buffer, fetching the first instruction loop, optimizing one or more instructions corresponding to the first instruction loop to generate a first optimized internal instruction loop, and storing the first optimized internal instruction loop in the loop buffer based on the determination that the first internal instruction loop is not stored in the loop buffer.

Abstract: Embodiments described herein provide an apparatus, computer readable digital storage medium and method for producing an instruction sequence for a computation unit which can be controlled by a program which includes at least the instruction sequence.

Abstract: A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.

Abstract: Described herein are devices and methods for implementing a transceiver with independently controlled components. The components may include a programmable digital portion, a dedicated digital portion, and an analog portion. Each independently controlled component includes a programmable controller that resides in the programmable digital portion of the component that controls components in the dedicated digital or analog portions using state transition information.

Abstract: Disclosed are an asynchronous pipeline system, a stage, and a data transfer mechanism. The asynchronous pipeline system having a plurality of stages based on a 4-phase protocol, includes: a first stage among the plurality of stages; and a second stage among the plurality of stages connected next to the first stage, wherein the first stage transmits and the second receives bundled data and control data through an always bundled data channel and on-demand data through an on-demand data channel according to need of the second stage.

Abstract: A multiplexing auxiliary processing element (PE) performs a process that includes the operations of receiving signals of a plurality of upstream processing elements (PEs) including a plurality of pairs of PEs arranged on the input side; supplying the signals from the upstream PEs to a multiplex PE that is multiplexed and used so that the signals are subjected to a predetermined process by the multiplex PE; receiving the processed signals subjected to the predetermined process by the multiplex PE and sequentially supplying the signals to a plurality of downstream PEs arranged on the output side; and performing operations of the upstream PEs synchronously with the supply of the processed signals to the corresponding downstream PEs on the basis of setting of the multiplexing auxiliary PE.