Abstract: An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The B16×16 tile is a nesting of a B2×2 tile that includes a two by two array of four B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. The expressway routing channels M1, M2, and M3 are segmented, and between each of the segments in the expressway routing channels M1, M2, and M3 are disposed extensions that can extend the expressway routing channel M1, M2, or M3 an identical distance along the same direction. The expressway routing channels M1, M2, and M3 run both vertically through every column and horizontally through every row of B2×2 tiles.

Abstract: A configurable interconnect for use with high-speed electronic system components. The interconnect uses a lightweight protocol with control characters embedded into the data stream. The control characters define events such as end of packet, end of packet with error, transmit on, transmit off, synchronizing codes, and pass-through status. In one described embodiment, the protocol is used in an internetworking device node in which a pair of high-speed counter rotating rings transport data packets. The high-speed interconnect permits data packets to pass through the node without the delays which might otherwise be experienced with time division multiplex bus structures and the like.

Abstract: An arrangement includes at least one data storage device, an automation controller, and an enhanced interface. The data storage device is connected to a computer and arranged to perform a plurality of operations in response to one or more commands received from the computer. The automation controller is configured to physically provide the data storage device with at least one data storage media. The enhanced interface operatively couples the data storage device with the automation controller, such that the data storage device can be selectively controlled by the automation controller and the automation controller can be selectively controlled by the data storage device depending on the received commands. The enhanced interface includes a standard serial interface and at least one additional line. The additional line is configured to provide a directing signal from the data storage device to the automation controller.

Abstract: A multiplexed bus data transmission control system, suitable for a multiplexed bus data flow control, according to the invention. The system includes a bus flow monitor, a critical value controller and a transmission control unit. The bus flow monitor is used to calculate the data flow of the multiplexed bus and to output a calculated result according to a time constant. The critical value controller receives the calculate result and outputs a corresponding critical value according to a ratio of the calculated result and the time constant. The transmission control unit is used to control a data transmission device using the multiplexed bus according to the critical value outputted from the critical value controller.

Abstract: A computer system having bus controller operating code stored in a non operating system managed, extended portion of system memory. In one example, the operating code is executed by a bus controller for a computer bus conforming to the Universal Serial Bus (USB) specification. In one example, the bus controller operating code is stored in a portion of system memory that is located above the top system memory address reported to the operating system, thereby hiding the stored code from the operating system. In one example, the bus controller operating code is constructed during the startup of the computer system with a code construction routine. Storing bus controller operating code in a non operating system managed, extended portion of system memory provides a computer system greater flexibility in system memory usage.

Abstract: A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.