Patents Examined by Benjamin T Liu
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Patent number: 10388570Abstract: A method of forming a semiconductor structure includes forming a fin region and a non-fin region surrounding the fin region in a substrate, wherein sidewalls of the fin region comprise a stepped height structure comprising an outer portion adjacent to the non-fin region with a first height and an inner portion with a second height greater than the first height. The method also includes forming a plurality of fins disposed over a top surface of the inner portion of the fin region, forming an isolation layer disposed over the top surface of the inner portion of the fin region surrounding a portion of the sidewalls of the plurality of fins, and forming a fin liner disposed (i) between the isolation layer and the top surface of the inner portion of the fin region and (ii) between the isolation layer and the portion of the sidewalls of the plurality of fins.Type: GrantFiled: December 18, 2017Date of Patent: August 20, 2019Assignee: International Business Machines CorporationInventors: Peng Xu, Kangguo Cheng
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Patent number: 10374155Abstract: An electrically actuated switch comprises a first electrode, a second electrode, and an active region disposed therebetween. The active region comprises at least one primary active region comprising at least one material that can be doped or undoped to change its electrical conductivity, and a secondary active region comprising at least one material for providing a source/sink of ionic species that act as dopants for the primary active region(s). Methods of operating the switch are also provided.Type: GrantFiled: July 18, 2017Date of Patent: August 6, 2019Assignee: Hewlett Packard Enterprise Development LPInventor: R. Stanley Williams
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Patent number: 10373960Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.Type: GrantFiled: December 18, 2017Date of Patent: August 6, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Daeik Kim, Semyeong Jang, Jemin Park, Yoosang Hwang
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Patent number: 10347545Abstract: There is provided a method for producing on a same substrate at least one first transistor and at least one second transistor that have different characteristics, the method including producing at least one first gate pattern and at least one second gate pattern on the substrate; depositing, on the first and the second gate patterns, at least: a first protective layer, and a second protective layer overlying the first protective layer and made of a material different from that of the first protective layer; masking of the second gate pattern by a masking layer; isotropic etching of the second protective layer; removing the masking layer; and anisotropic etching of the second protective layer selectively relative to the first protective layer.Type: GrantFiled: May 19, 2017Date of Patent: July 9, 2019Assignee: COMMISSARIAT A L'ENERGIE ATOMIOUE ET AUX ENERGIES ALTERNATIVESInventors: Laurent Grenouillet, Sebastien Barnola, Marie-Anne Jaud, Jerome Mazurier, Nicolas Posseme
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Patent number: 10332950Abstract: An organic light emitting display device includes a folding part configured to be folded, and a flat part adjacent to the folding part. The folding part includes a first pixel. The flat part includes a second pixel. The first pixel includes a first organic light emitting diode, a first driving transistor and a first control transistor. The first driving transistor includes a first semiconductor pattern. The first control transistor includes a second semiconductor pattern. The second pixel includes a second organic light emitting diode, a second driving transistor and second control transistor. The second driving transistor includes a third semiconductor pattern. The second control transistor includes a fourth semiconductor pattern. At least one of the first or second semiconductor patterns includes an oxide semiconductor or a polycrystalline silicon, and each of the third and fourth semiconductor patterns includes the other of the oxide semiconductor and the polycrystalline silicon.Type: GrantFiled: August 23, 2017Date of Patent: June 25, 2019Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Changyong Jeong, Heejun Kwak, Taewook Kang, Mugyeom Kim, Jaeseob Lee, Jonghan Jeong
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Patent number: 10325824Abstract: At least one method, apparatus and system are disclosed for controlling threshold voltage values for a plurality of transistor devices. Determine a first threshold voltage of a first transistor gate comprising a first gate channel having a first length. Determine a second length of a second gate channel of a second transistor gate. Determining a process adjustment of the second gate based on the second length for providing a second threshold voltage of the second transistor gate. The second threshold voltage is within a predetermined range of the first threshold voltage. Provide data relating to process adjustment to a process controller for performing the process adjustment.Type: GrantFiled: June 13, 2017Date of Patent: June 18, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Mitsuhiro Togo, Ram Asra, Xing Zhang, Palanivel Balasubramaniam
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Patent number: 10304683Abstract: By decoupling the formation of a metal silicide in the gate electrode structure and the raised drain and source regions, superior flexibility in designing transistor elements and managing overall process flow may be achieved. To this end, the metal silicide in the gate electrode structures may be formed prior to actually patterning the gate electrode structures, while, also during this process sequence, a mask material may be applied for reliably covering any device regions in which a silicidation is not required. Consequently, superior gate conductivity may be accomplished, without increasing the risk of silicide penetration into the channel region of sophisticated fully depleted SOI transistors.Type: GrantFiled: December 18, 2017Date of Patent: May 28, 2019Assignee: GLOBALFOUNDRIES Inc.Inventor: Elliot John Smith
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Patent number: 10304995Abstract: A flexible electric device includes a first electrode on a flexible member, at least one semiconductor element on the first electrode, at least one filling region adjacent to the semiconductor element and a second electrode on the semiconductor element.Type: GrantFiled: March 6, 2014Date of Patent: May 28, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-hee Choi, Yun-seong Lee
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Patent number: 10290688Abstract: The present invention provides an AMOLED device and a manufacturing method thereof. The manufacturing method of the AMOLED device according to the present invention adopts an ink jet printing operation to form an anode of the AMOLED device and thus, compared to the prior art operations, saves one mask and reduces one round of photoengraving thereby simplifying the manufacturing operation of the AMOLED device and lowering the manufacturing costs. The AMOLED device according to the present invention comprises an anode that is formed through an ink jet printing operation, so that the manufacturing operation is simplified and the manufacturing cost is reduced.Type: GrantFiled: December 16, 2016Date of Patent: May 14, 2019Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Baixiang Han, Yuanchun Wu
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Patent number: 10283518Abstract: A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern.Type: GrantFiled: May 20, 2014Date of Patent: May 7, 2019Assignee: SK hynix Inc.Inventors: Ki Hong Lee, Seung Ho Pyi, Seung Jun Lee
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Patent number: 10276491Abstract: A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of the at least one device. In various embodiments, a selective etching process is performed to remove the second dielectric layer and expose the contact metal layer, without substantial removal of the first dielectric layer. In some examples, a metal VIA layer is deposited over the at least one device. The metal VIA layer contacts the contact metal layer and provides a local interconnect structure. In some embodiments, a multi-level interconnect network overlying the local interconnect structure is formed.Type: GrantFiled: August 31, 2016Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shang-Wen Chang, Yi-Hsiung Lin
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Patent number: 10263042Abstract: An organic photoelectric device includes a first electrode and a second electrode facing each other, and an active layer between the first electrode and the second electrode, wherein the active layer includes an n-type semiconductor compound that is transparent in a visible ray region and represented by Chemical Formula 1, and a p-type semiconductor compound having a maximum absorption wavelength in a wavelength region of about 500 nm to about 600 nm of a visible ray region.Type: GrantFiled: September 2, 2016Date of Patent: April 16, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Rie Sakurai, Hiromasa Shibuya, Tadao Yagi, Kwang Hee Lee, Takkyun Ro, Sung Young Yun, Gae Hwang Lee, Dong-Seok Leem, Seon-Jeong Lim, Xavier Bulliard, Yong Wan Jin, Yeong Suk Choi, Hye Sung Choi
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Patent number: 10256347Abstract: The semiconductor device includes an oxide semiconductor layer including a plurality of channel formation regions arranged in the channel width direction and parallel to each other and a gate electrode layer covering a side surface and a top surface of each channel formation region with a gate insulating layer placed between the gate electrode layer and the channel formation regions. With this structure, an electric field is applied to each channel formation region from the side surface direction and the top surface direction. This makes it possible to favorably control the threshold voltage of the transistor and improve the S value thereof. Moreover, with the plurality of channel formation regions, the transistor can have increased effective channel width; thus, a decrease in on-state current can be prevented.Type: GrantFiled: July 5, 2017Date of Patent: April 9, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 10249586Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.Type: GrantFiled: September 21, 2017Date of Patent: April 2, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles L. Arvin, Christopher D. Muzzy
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Patent number: 10243005Abstract: An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer which each have a shape whose end portions are located on an inner side than end portions of the semiconductor layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is provided between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected in an opening provided in a gate insulating layer through an oxide conductive layer.Type: GrantFiled: September 15, 2016Date of Patent: March 26, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Junichiro Sakata, Masayuki Sakakura, Yoshiaki Oikawa, Kenichi Okazaki, Hotaka Maruyama
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Stacked film, electronic device substrate, electronic device, and method of fabricating stacked film
Patent number: 10211043Abstract: A stacked film is a stacked film including an oxide film, and a metal film provided on the oxide film, in which the oxide film includes a ZrO2 film of which a main surface is a (001) plane, the metal film includes a Pt film or a Pd film that has a single orientation and of which a main surface is a (001) plane, and a [100] axis of the ZrO2 film and a [100] axis of the metal film are parallel to an interface between the oxide film and the metal film, and the axes of both are parallel to each other.Type: GrantFiled: May 19, 2017Date of Patent: February 19, 2019Assignee: TDK CORPORATIONInventors: Takao Noguchi, Yoshihiko Yano -
Patent number: 9287392Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.Type: GrantFiled: November 28, 2012Date of Patent: March 15, 2016Assignee: Pannova Semic, LLCInventors: Tsutomu Oosuka, Hisashi Ogawa, Yoshihiro Sato
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Patent number: 8889539Abstract: A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.Type: GrantFiled: December 11, 2008Date of Patent: November 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-In Ryu, Bong-Su Kim, Dae-Ik Kim, Ho-Jun Lee, Dae-Young Jang, Si-Hyung Lee