Abstract: A method and system for processing a substrate in the presence of high purity C.sub.5 F.sub.8. When processing oxides and dielectrics in a gas plasma processing system, C.sub.5 F.sub.8 is used in combination with a carrier gas (e.g., Ar) and one or more of CO and O.sub.2. When using a silicon nitride (Si.sub.x N.sub.y) layer as an etch stop, effective etching is performed due to the selectivity of oxides versus silicon nitride. The method is used when etching down to self-aligning contacts and other layers. The method may be practiced with or without using an anti-reflective coating underneath the photoresist layer.

Abstract: A method of forming a field oxide or an isolation region in a semiconductor die. An oxidation mask layer (over an oxide layer disposed over the substrate) is patterned and subsequently etched, preferably so that the oxidation mask layer may have a nearly vertical sidewall. The oxide layer and the substrate in the isolation region are etched to form a recess in the substrate having a sloped surface with respect to the sidewall of the oxidation mask layer. A field oxide is then grown in the recess using a dry oxidizing atmosphere. The sloped sidewall of the substrate recess effectively moves the face of the exposed substrate away from the edge of the oxidation mask layer sidewall. Compared to non-sloped techniques, the oxidation appears to start with a built-in offset from the patterned etch. This leads to a reduction of oxide encroachment and less field oxide thinning. The preferred range of slopes for the substrate sidewall is from approximately 10.degree. to 40.degree.

Abstract: A thick plated interconnect (80) may be fabricated by forming a metal layer (20) above a semiconductor layer (12). A dielectric layer (22) may be formed on the metal layer (20). A via (24) may be formed in the dielectric layer (22) to expose the metal layer (20). A copper lead (50) may be formed electrically coupled to the metal layer (20) through the via (24) of the dielectric layer (22). A barrier member (88) may be formed on the copper lead (50). A bondable member (86) comprising aluminum may be formed on the barrier member (88).

Abstract: A process for structuring a movable element out of a membrane region. A sacrificial layer and a sealing layer are applied to the underside of the membrane region. Following removal of the sacrificial layer, sealing layer forms a limit stop and a seal for the movement of the movable element.

Abstract: A method for etching a platinum (Pt) layer of a semiconductor device is provided which improves the etching slope of a sidewall of the platinum layer used as a storage node of the semiconductor device. The semiconductor device consists of a semiconductor substrate including a bottom layer on which various other layers are formed. Specifically, according to this invention, a Pt layer is formed on a bottom layer of a semiconductor substrate. An adhesive layer is then formed on the Pt layer while a mask layer is formed on the adhesive layer. After formation of the various layers, the mask layer and adhesive layer are patterned using an etching process to form a mask pattern and an adhesive layer mask pattern, respectively. The semiconductor substrate is then heated and an etching process is performned on the Pt layer using the mask pattern and the adhesive layer mask pattern to form etching slope sidewalls of the Pt layer having etching slopes close to vertical.

Abstract: A method of fabricating an unlanded metal via of multi-level interconnection. The method is characterized by utilizing damascene scheme to form a metal wiring layer so that the processes are simplified. Moreover, by this method of the invention, a problem of difficulty in filling dielectric material between the metal wiring lines can be avoided and the metal layer does not have to be etched prior to filling the dielectric material. Further more, an etching stop layer is formed over the first inter-metal dielectric layer to avoid overetching during the formation of metal via, which therefore avoid short circuit. Forming the metal wiring lines by damascene scheme allows the etching stop layer to be easily formed over the first dielectric layer, without over etching the metal via.

Abstract: A etchant recipe including a mixed gas of one of a CH.sub.x F.sub.y group and CO gas is used to etch a silicon nitride layer by plasma etching so as to form a thin polymer layer to protect a silicon layer under the silicon nitride layer from over-etching. Then a soft etching is performed to remove the thin polymer. The etchant recipe is, for example, used in forming a contact opening on a gate of a MOS transistor, on which a silicon nitride layer is formed.

Abstract: A channel layer is formed in a surface of a semiconductor substrate, and a plurality of trenches are formed in the surface of the semiconductor substrate, the trenches being deeper than the channel layer. Then, gate electrodes are formed in the trenches, respectively, after which body layers are formed between the trenches and source layers are formed adjacent to the trenches.

Abstract: Compositions of ammonium fluoride, propylene glycol, and water and methods of using these compositions to remove etch residues from silicon substrates which result from plasma or reactive ion etching of silicon substrate are provided. Not only do the compositions of the present invention overcome the environmental concerns associated with the use of ethylene glycol, but unlike previous compositions of ammonium fluoride in propylene glycol which are acidic, the compositions of the present invention are neutral to slightly basic (i.e., pH 7 to about pH 8). Hence, they remove etch residues from silicon substrates with minimal attack on other features on the silicon substrates.

Abstract: A method for forming a dual damascene structure on a substrate is disclosed.