Abstract: A spread PN code signal receiver having a delay locked loop (DLL) circuit in an IF or RF stage characterized in that correlation outputs to be used for the DLL circuit control are (1) a correlation output between (a) a PN code advanced in phase with respect to the received signal and (b) the received signal and (2) a correlation output between (a) a PN code delayed in phase with respect to the received signal and (b) the received signal. The correlation outputs are used to detect the lock/unlock signal in the DLL circuit. In particular, AND logic for these two correlation outputs is employed to generate the lock/unlock signal only when the DLL circuit is perfectly synchronized in phase with the received signal. With this feature, a lock state can not de detected unitl a stable lock state is obtained.