Abstract: Techniques of shallow trench isolation and devices produced therefrom are provided. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device.

Abstract: A trench is formed by forming a photoresist film on a second interlevel insulator and performing isoprotonic etching using the photoresist film as a mask. A lower electrode layer made of platinum (Pt), a dielectric film made of a dielectric material and an upper electrode layer made of platinum (Pt) are formed in this order by, for example, a CVD method respectively. Further, the lower electrode layer and the upper electrode layer are selectively removed by a CMP method except for the trench with the second interlevel insulator as an end point detection layer, flattening the surface at the same time. Accordingly, a capacitor having a structure which has a flat surface comprised of both edges of the lower electrode layer and the dielectric film, and the upper electrode layer is formed in the trench of the second interlevel insulator respectively.

Abstract: A method for removing black silicon in semiconductor fabrication is disclosed. First, a trench is formed in a semiconductor substrate having a pad dielectric layer and a hard mask layer. Then, the hard mask layer is removed. A photoresist layer covers the trench and only black silicon created at the edge of the semiconductor substrate during formation of the trench is left uncovered. Finally, the black silicon is removed.

Abstract: A dual damascene process and structure for fabricating semiconductor devices are disclosed. In one embodiment of the invention, a protection layer is deposited on top of a metal layer to protect the metal layer during subsequent etching of an oxide layer to form the via and damascene trench. Because the selectivity between the oxide layer and the protection layer is high, the number and complexity of processing steps are thereby reduced. Other embodiments of the present invention use a metal sealant layer and/or anti-reflective coating in conjunction with the protection layer in a dual-damascene process.

Abstract: Exemplary embodiments are directed to providing a flash EEPROM technology which is compatible with deep submicron dimensions, and which is suitable for straightforward integration with high performance logic technologies. Unlike known technologies, exemplary embodiments provide a reduced cell area size in a split gate cell structure. An exemplary process for implementing a flash EEPROM in accordance with the present invention involves growing a tunneling oxide in a manner which reduces tunneling barrier height, and requires minimum perturabition to conventional high performance logic technologies, without compromising logic function performance.