Abstract: A system for providing an accurate interference value signal received over a channel and transmitted by an external transceiver. The system includes a first receiver section for receiving the signal, which has a desired signal component and an interference component. A signal extracting circuit extracts an estimate of the desired signal component from the received signal. A noise estimation circuit provides the accurate interference value based on the estimate of the desired signal component and the received signal. A look-up table transforms the accurate noise and/or interference value to a normalization factor. A carrier signal-to interference ratio circuit employs the normalization factor and the received signal to compute an accurate carrier signal-to-interference ratio estimate. Path-combining circuitry generates optimal path-combining weights based on the received signal and the normalization factor.

Abstract: In a serial data transmission apparatus connected to a data transmission bus, an edge detector detects an edge in a signal at the data transmission bus. An edge interrupt operation is carried out to operate a timer in response to the edge. The edge interrupt operation is stopped when the timer is being operated. A timer interrupt operation carries out a fetching operation of a bit data on the data transmission bus in a receiving mode or a transmitting operation of a bit data to the data transmission bus in a transmitting mode, in response to the timer means whose content reaches a predetermined value.

Abstract: Disclosed is a digital pulse shaping circuit for reducing undesirable frequency components in subsequent data modulated transmissions, which circuit can be easily manufactured as a monolithic integrated circuit. In a preferred embodiment, the pulse shaping circuit employs an edge detector circuit to detect data transitions of an incoming serial data stream. Upon a data edge detection, the edge detector provides a control signal to a digital counter to enable the counter to begin counting applied clock pulses and generate a linear count. The linear count is provided to a decoding circuit, which generates an output word as a nonlinear function of the value of the count. The decoded output word then drives a digital modulator which modulates an RF carrier to provide wireless data transmission with improved spectral efficiency.

Abstract: A method for determining a phase error in a radio-frequency signal received by a receiver, wherein an impulse response of a received signal is calculated, measuring points are chosen from the signal, and samples are taken from the surrounding areas of the measuring points. The samples are filter with a complex adapted filter. A phase error in the samples is measured from the filtering result, and the total phase error in the received signal is calculated on the basis of the measured phase error. In order to be also able to measure large phase errors, the measuring points are chosen on the basis of phase errors measured from signals received earlier, in such a manner that the phase error at the measuring points remains within predetermined limits. The receiver includes a compensator for the phase and frequency errors in the received signal.

Abstract: In a method for receiver-side clock recovery for digital signals having a constant bit rate following cell-structured, asynchronous transmission with pauses of different length between individual cells using the loading state of an FIFO memory into which the received digital signals are written, at the start of a transmission the digital signals are initially read with a received clock into the FIFO memory holding multiple cells of the received signals until the FIFO memory is half filled. The digital signals written into the FIFO memory are read out with a readout clock whose frequency is smaller than the frequency of the received clock. During the readout a signal for controlling the frequency of the readout clock is derived from the respective loading state of the FIFO memory.

Abstract: The goal of this invention is to offer an orthogonal modulator circuit where carrier feedthrough of the direct modulation method does not occur and there are not the two output frequencies of the indirect modulation method. A signal with the first frequency (.omega..sub.c1) enters a first and a second modulator 30, 40 and becomes two reciprocal 90.degree. phase shifted, four phase modulated signals S.sub.1, S.sub.2 that enter a first and a second mixer circuit 51, 52; a signal with the second frequency (.omega..sub.c2) is multiplied with the two 90.degree. phase shifted signals, and the output of the first and second mixer are added together in a SSB modulator resulting in the output of a single frequency signal.

Abstract: Convergence of blind fractionally spaced equalizers is improved, and misconvergence is corrected by training the equalizers to detect convergence of one adaptive filter, copying the tap weights of the converged adaptive filter to the other adaptive filters and shifting the tap weights of the other adaptive filters according to the expected phase difference between the respective filters. In a two-dimensional orthogonal modulation scheme the converged weights of a first filter are copied to a second filter and shifted .pi./2. For the two dimensional orthogonal modulation scheme, the probability of a proper convergence can be increased by choosing initial tap weights for the two adaptive filters with a 3.pi./4 phase difference.

Abstract: A phase synchronizing apparatus that operates with a low power consumption so as to be particularly suited for use in battery powered data communications situations. The phase synchronizing apparatus receives reception data containing a data code portion synchronous with a transmission clock of a predetermined frequency and produces a reception clock synchronous with the transmission clock. The phase synchronizing apparatus uses a synchronization counter and a compensation circuit to achieve the phase synchronization. The invention can also be implemented as a decoder for decoding data received from a data transmission or as an integrated circuit for data communication.

Abstract: The Manchester coder/decoder of the invention includes the following modules. A synchronization signal generation module (11), gives the clocks' start signal. A module (12) for the synchronization and generation of clocks generates the transmission/coding and decoding clocks and a low frequency clock. A decoding module (13) includes a flip-flop driven by the decoding clock. The decoding is a simple sampling of the input signal of the Manchester coded data which is to be decoded during the reception phase. A coding module (14) carries out an "OR EXCLUSIVE" function between the input signal to be coded in Manchester code and the transmission clock.

Abstract: An apparatus and method for demodulating a frequency-shift keyed (FSK) signal to provide a data signal. An input FSK signal is processed in a waveform reshaper to generate a first pulse signal which includes a pulse for each cycle of the FSK signal. The first pulse signal is processed in a cycle counter to generate second and third pulse signals. The second pulse signal includes a pulse for each time a low clock pulse count is reached between pulses of the first pulse signal, and the third pulse signal includes a pulse for each time a high clock pulse count is reached between pulses of the first pulse signal. The low and high pulse counts are generally indicative of cycles of first and second FSK carrier frequencies, respectively, in the input FSK signal. The second pulse signal is processed in a data recognizer to generate a logic level indicator signal.

Abstract: A frame synchronization apparatus is applied to the TDMA (Time Division Multiple Access) communication system, particularly, where a plurality of transmission rates are available. The frame synchronization apparatus calculates correlations between sampled sequences of a received signal and an assigned sync sequence during the longest or shortest frame period in the plurality of transmission rates. The apparatus stores positions where the correlations exceed a given threshold. Then, the apparatus sets a search gate at a position after a lapse of the longest or shortest frame period from each of those positions. The apparatus calculates correlations between the sync sequence and sampled sequences of the received signal for all the search gates. The actual transmission rate is determined from the plurality of transmission rates based on a time interval of positions where the correlations beyond a second threshold were detected. Synchronization is thus established.

Abstract: The digital processing apparatus includes a high speed response PLL that produces a first clock signal locked on the horizontal synchronization signal included in the video signal input thereto. An analog to digital converter converts the input video signal with respect to the first clock signal into a digitized video signal. A write controller controls a video memory to store the digitized video signal based on the first clock signal. A low speed response PLL produces a second clock signal based on the vertical synchronization signal included in the video signal. A read controller controls the video memory to read out the stored digitized video signal therefrom based on the second control signal. The digital processing apparatus can store and read the digitized video signal to and from the video memory stably, enabling the video signal read from the video memory to be processed effectively and securely.

Abstract: A waveform shaping circuit includes an input terminal, an output terminal, and a plurality of cascaded circuit stages. Each of the cascaded circuit stages includes a delay circuit having an output and an input, a current source, and a switch circuit, connected electrically to the output of the delay circuit and controlled by the delay circuit, for connecting electrically the current source to the output terminal. The input of the delay circuit of a first one of the circuit stages is connected electrically to the input terminal. The input of the delay circuit of remaining ones of the circuit stages is connected electrically to the output of the delay circuit of an immediately preceding one of the circuit stages. The delay circuits have equal delay times. The total delay time provided by the delay circuits of the circuit stages is equal to or is a multiple of half a bit time of the fundamental data rate.