Abstract: A method for fabricating a composite semiconductor from a plurality of substantially identical individual semiconductor devices formed on a common semiconductor wafer includes testing the devices on the wafer to generate a positional mapping of acceptable and non-acceptable devices, dividing the wafer into a plurality of areas of arbitrary size, connecting corresponding contact pads on only the acceptable devices within a given area to each other via common conductive paths which are supported on a dielectric film covering the pads, the film having appropriately located holes filled with conductive material to electrically couple the common conductive paths and the underlying contact pads of only the acceptable devices. The devices within a given area are intercoupled in a manner to form an operational array; single or multiple arrays may be coupled together to form a composite package having common external contacts and heat sink supports.

Abstract: A process for forming individual dies having faces that allow the dies to be assembled against other like dies to form one and/or two dimensional scanning arrays wherein the active side of a wafer is etched to form small V-shaped grooves defining the die faces, relatively wide grooves are cut in the inactive side of the wafer opposite each V-shaped groove, and the wafer cut by sawing along the V-shaped grooves, the saw being located so that the side of the saw blade facing the die is aligned with the bottom of the V-shaped groove so that there is retained intact one side of the V-shaped groove to intercept and prevent cracks and chipping caused by sawing from damaging the die active surface and any circuits thereon.

Abstract: An encapsulated die package (20) is shown in which a semiconductor die is connected in a die-attach aperture of a copper foil tape (11). Die contact pads (31) are bonded to the inner ends (31a) of interconnected finger contacts (13) on the tape. Finger contacts etched in the foil include splayed out portions (15) extending to probe ends (19). Interconnect cross-links (16) initially connect the finger contacts and the tape edges and function as dam bars in subsequent encapsulation steps. The die and die bonds are mold encapsulated to form the die package (20) and a carrier frame (17) is simultaneously molded around and spaced from the periphery of package (20). The probe ends are exposed within a slot (34) in the frame or extend from the ends of the frame so that probe tips can be pressed thereon to test the die and its bonds. Prior to testing, the interconnects exposed in the annulus between the package and the carrier are blanked out so that each finger leading from a die contact pad becomes discrete, i.e.

Abstract: The method of forming a multiwafer integrated circuit for abutting electrical connection to external electronics is disclosed. The method comprises forming a plurality of grooves in the first surface of each of first and second wafers. The grooves are filled with a body of insulating material and joined along the groove surfaces thereof. In one embodiment active circuitry is formed in one of the abutting wafer surfaces. In another embodiment active circuitry is formed in a non-abutting surface of one of the wafers. Conductive leads are applied to the surface of one of the wafers to be in electrical communication with the doped regions. At least one of the conductive leads extends across at least a portion of the grooves. The wafers are trimmed in length so that the lengthwise edges of the wafers are defined by the grooves and the butt end of at least one of the conductive leads is exposed.

Abstract: A method of fabricating a field-effect transistor is disclosed wherein only two masking steps are used in the development of the device. The semiconductor wafer used in the process has a non-alloyed contact at its top surface, that is, a contact which does not require alloying temperatures in excess of 200 degrees C. The first mask is used to create conventional mesa structures which isolate each individual field-effect transistor from its adjacent neighbors. A second mask is utilized to define the source and drain electrodes and also to create a gap through which the gate electrode structure is fabricated. By using a single mask for creation of both the source and drain electrodes and the gate structure, very close tolerances are obtained between the gate structure and the source and drain regions.

Abstract: A method is described for coupling the leadframe of a thermogenetic semiconductor device to a heatsink. This method consists of screening a first layer of thermally conductive epoxy on the heatsink. The first layer is cured and a second layer is screened on the first layer. The leadframe is then deposited on the second layer and the second layer is cured. The device then goes to encapsulation and final processing.

Abstract: An improved patterning process, useful for the metallization of highly efficient photovoltaic cells, the formation of X-ray lithography masks in the sub half-micron range, and in the fabrication of VLSI and MMIC devices, is disclosed. The improved patterning process includes the steps of providing a substrate with a photoactive layer, patterning the photoactive layer with an inclined profile, depositing on both the substrate and the patterned photoactive layer a layer of disjointed metal such that the thickness of the metal layer exceeds that of the patterned photoactive layer and that the metal layer deposited on the substrate is formed with walls normal to the surface of the substrate. Preferably, the deposition of the disjointed metal layer is effected by evaporative metallization in a direction normal to the surface of the substrate. The deposited metal layer on the substrate is characterized by a high aspect ratio, with a rectangular cross section.

Abstract: A semiconductor device and a method for manufacturing a semiconductor device of a type having a resin package and a window in the package such as a quartz glass window transparent to ultraviolet rays. A semiconductor chip is bonded onto a surface of a die pad of a lead frame. A softened resin is then extruded from the opposite surface of the die pad through gaps between the die pad and the leads with the extrusion being carried out in an inert gas atmosphere. An inner package member is thus formed surrounding the semiconductor chip. An outer package member, made of a thermosetting resin having a weight ratio of resin to filler less than that of the inner package, is molded around the chip assembly and inner package.

Abstract: The present invention is directed to a process of forming a package for enclosing an electrical device wherein the enclosure contains a very low amount of oxygen and water vapor. The package includes a base and lid components bonded together by a sealing glass. The lid component contains a gettering alloy from which the oxide layer is removed prior to the final sealing of the package. The gettering alloy forms a refractory oxide layer under an oxide layer formed with the primary constituent of the alloy.

Abstract: There is disclosed a film field effect transistor which can be operated at fast switching rates for use, for example, in video display applications. The transistor includes a body of silicon semiconductor material having a structure more ordered than amorphous material and less ordered than single crystalline material. The source and drain of the transistor comprise rectifying contacts formed on the body of silicon semiconductor material. Also disclosed are a method of making the transistor and an electronically addressable array system utilizing the transistor to advantage.

Abstract: A method of manufacturing optocoupler devices is provided wherein individual light emitting chips are mounted to a plurality of photodetector chips still in wafer form such that testing of the emitter detector pairs may be accomplished prior to dicing of the photodetector chip and mounting of the emitter detector pairs.

Abstract: A method for forming a layer of silicon dioxide over a silicon island on an insulating surface wherein the layer on top of the island is thinner than on the sidewalls is disclosed. The silicon island is oxidized and a silicon layer is deposited thereover. The layer of silicon is oxidized and the oxide layer is anisotropically etched until the top surface of the island is exposed, leaving oxide only on the sidewalls of the island. The exposed portion of the island is then oxidized to form a thin layer of gate oxide thereon. A conductive polycrystalline silicon electrode is deposited on the oxide-covered island. The disclosed method is particularly useful in the formation of MOSFETs.