Patents Examined by Blake Betz
  • Patent number: 7106331
    Abstract: A system, method, and computer program product for performing edits on related curves by automatically defining an associative entity that is upstream of either curve being connected. The connecting entity is called an ‘intermediary’. When creating a connection between curves, irrespective of where they appear in the associative tree, their geometry is made dependent on a common intermediary that is placed upstream of both curves in the tree. With this structure, both curves are related to the intermediary but retain all the properties of being connected to each other. Any edit performed to either curve is redirected through the intermediary such that both curves are simultaneously modified, providing the user with bi-directional propagation of edits. The user does not need to keep track of the order that the curves were related.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: September 12, 2006
    Assignee: UGS Corp.
    Inventors: Aditya N. Gurushankar, Daniel C. Staples, Joseph J. Bohman, Prasad Pingali, Ganapathy S. Kunda, Navinchandra Pai
  • Patent number: 7038697
    Abstract: A system and method for generating color gradients is provided. The system generates color gradients using techniques from geometric surface modeling. The system and method of the present invention allow designers to specify very complex gradients in a simple way. The system can employ, for example, a vector-based interpolation method and/or a pixel-based partial differential equation (PDE) interpolation methods to facilitate generation of the color gradients. In one example, input boundary curves and/or feature curves are approximated by line segments, which are then utilized to generate a triangulation approximating a smooth color gradient.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: May 2, 2006
    Assignee: Microsoft Corporation
    Inventors: Michel J. Gangnet, Michael Kallay, Andrew Y. Wu, Eric J. Stollnitz, Devon L. Strawn, John Michael Lounsbery, Patrick Pérez
  • Patent number: 6992707
    Abstract: A digital video camera system may utilize a joint video and still image pipeline that simultaneously acquires, processes, transmits and/or stores digital video and high resolution digital still image photographs. The joint pipeline may include a video pipeline optimized for digital video frames and a high resolution still image pipeline optimized for high resolution digital still images. The digital video camera system may also concurrently acquire and process video frames and high resolution still image in burst mode using delayed encoding technology.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: January 31, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Pere Obrador
  • Patent number: 6950103
    Abstract: Automatically positioning of typographical features, such as vertical stems or horizontal segments of a character, on high contrast pixel sub-component boundaries as part of a rendering process that uses separately controllable pixel sub-components of pixels to represent different portions of the character. In order to identify the typographical features of the character that are to be aligned with high contrast pixel sub-component boundaries, topology of the character is analyzed at runtime. In display devices having vertical stripes of same-colored pixel sub-components, character legibility is increased when the left edges of stems are aligned with high contrast boundaries between pixel sub-components. Processing time and resources are conserved by performing a partial, rather than a full, topological analysis of the character.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: September 27, 2005
    Assignee: Microsoft Corporation
    Inventors: Beat Stamm, Gregory C. Hitchcock, Claude Betrisey, Matt Conway
  • Patent number: 6947056
    Abstract: An apparatus generally having a register, an adder circuit and a mask circuit is disclosed. The register may be configured to replace a current value with a new value in response to a clock value. The adder circuit may be configured to generate the new value by adding the current value to a delta value. The mask circuit may be configured to mask at least one value among the delta value, the new value and the clock value in response to a mask value having a plurality of bits.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: September 20, 2005
    Assignee: LSI Logic Corporation
    Inventor: Mark J. Kwong
  • Patent number: 6927773
    Abstract: The invention provides a font processing device. In font enlargement, a target font to be enlarged or reduced is divided into columns or rows, and a cost is calculated based on the pixel pattern formation for each column and row. In enlargement processing, a cost represents a line segment volume, and a column or a row that has low-cost, that is, has a pixel array close to a line segment, is difficult to be enlarged. Further, in reduction processing, a cost represents a degree of likeness to an adjacent column or row, and a column or a row that has a similar pixel pattern is reduced with priority. In practice, the column or row for the target font is decided based on the pixel formation of the target font for enlargement or reduction so that natural enlargement/reduction can be obtained. In addition, font modification is executed by using enlargement and reduction of the font.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: August 9, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Yukinobu Momozono, Takashi Kurumisawa
  • Patent number: 6919890
    Abstract: A system and method of grid layout generates a fiducial graph for a grid or table in a given dimension and uses the fiducial graph to determine size preferences and fiducial positions of the grid and its grid elements along that dimension. Fiducial positions may include origin fiducials of grids and grid elements as well as fiducial positions of attached grid elements. Types of fiducial graphs include series-parallel fiducial graphs and non-series-parallel fiducial graphs (e.g., partially reduced fiducial graphs), which have different algorithms for computing size preferences and fiducial positions.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: July 19, 2005
    Assignee: Curl Corporation
    Inventor: Robert H. Halstead, Jr.
  • Patent number: 6870534
    Abstract: A method of simulating the effects of one or more explosive events utilizes a mapping of graphically-valued dots to describe the explosive event at detonation at a plurality of (x,y) positions. A degradation rule is applied to the mapping of dots at each of times tn, for n=1 to N, to yield corresponding mappings of degraded value dots. The degradation rule specifies how the mapping of dots at detonation changes with time. The mapping at detonation and mappings of the degraded value dots are then simultaneously displayed in (x,y) registration with one another.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: March 22, 2005
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Robert Woodall, Felipe Garcia