Abstract: Provided are methods of forming electric devices by effecting application of a stress to the device so as to deform the device within the device's elastic limit and to place the device into a new electric—e.g., resistance—state.

Abstract: Methods, systems, and devices for enabling the use of a special, generic, or standard substrate for similar system SIP assemblies are disclosed. The required customization, which is defined by a system's interconnecting scheme, is done during package assembly by creating appropriate connections using wire bonds on pads that are placed on the substrate and intentionally left open for purpose of customization. The wire bond links can be changed as required for a given system design.

Abstract: An image sensor chip includes a semiconductor layer intended to receive illumination on a back face and comprising a matrix of pixels on a front face. An interconnection structure is arranged on the front face and a carrier is attached to the interconnection structure with a first face of the carrier facing the front face. An annular trench, arranged on a perimeter of the image sensor chip, extends from a second face of the carrier through an entire thickness of the carrier and into the interconnection structure. A via opening, arranged within the annual trench, extends from the second face of the carrier through the entire thickness of the carrier to reach a metal portion of the interconnection structure. The via opening an annual trench are lined with an insulating layer. The via opening include a metal conductor making an electrical connection to the metal portion.

Abstract: A light emitting diode includes a support substrate; a light emitting structure including a second semiconductor layer, an active layer, and a first semiconductor layer; at least one groove formed on the lower surface of the light emitting structure; a second electrode located on at least the lower surface of the second semiconductor layer, and electrically connected with the second semiconductor layer; an insulating layer partially covering the second electrode and the lower surface of the light emitting structure, and including at least one opening corresponding to the at least one groove; and a first electrode electrically connected to the first semiconductor layer exposed to the at least one groove, and at least partially covering the insulating layer, wherein the second electrode includes a second contact layer including an ohmic contact layer, and the ohmic contact layer is disposed in the shape of a plurality of islands.

Abstract: An image sensor includes a photodiode disposed in a first semiconductor material to absorb photons incident on the image sensor and generate image charge. A floating diffusion is disposed in the first semiconductor material and positioned to receive the image charge from the photodiode, and a transfer transistor is coupled between the photodiode and the floating diffusion to transfer the image charge out of the photodiode into floating diffusion in response to a transfer signal. A source follower transistor with a gate terminal is coupled to the floating diffusion to output an amplified signal of the image charge in the floating diffusion. The gate terminal includes a second semiconductor material in contact with the floating diffusion, and a gate oxide is partially disposed between the second semiconductor material and the first semiconductor material. The second semiconductor material extends beyond the lateral bounds of the floating diffusion.

Abstract: A method is disclosed evaluating a silicon layer crystallized by irradiation with pulses form an excimer-laser. The crystallization produces periodic features on the crystallized layer dependent on the number of and energy density ED in the pulses to which the layer has been exposed. An area of the layer is illuminated with light. A microscope image of the illuminated area is made from light diffracted from the illuminated are by the periodic features. The microscope image includes corresponding periodic features. The ED is determined from a measure of the contrast of the periodic features in the microscope image.

Abstract: Methods are provided for selectively depositing Al and N containing material on a first conductive surface of a substrate relative to a second, dielectric surface of the same substrate. In some aspects, methods of forming an Al and N containing protective layer or etch stop layer for use in integrated circuit fabrication are provided.

Abstract: A packing method for a semiconductor device includes a step of preparing the semiconductor device that has a sealing body having a principal surface and a plurality of leads, and a step of preparing a base carrier tape that has a peripheral portion, a step portion, and a pocket portion. The method further includes a step of placing the semiconductor device in the pocket portion, a step of bonding a cover tape to the step portion in such a manner that the sealing body is pressed against the base carrier tape, and a step of winding the base carrier tape with the semiconductor device placed therein and with the cover tape bonded thereto, around a tape reel. The base carrier tape includes a principal surface of the peripheral portion, a principal surface of the step portion, and a principal surface of the pocket portion.

Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: forming a bottom oxide layer; forming a first conductive layer on the bottom oxide layer; forming a stack including alternately arranged second conductive layers and insulating layers on the first conductive layer; forming a first opening having a first cross-sectional width and penetrating through the stack and a portion of the first conductive layer; forming a second opening having a second cross-sectional width and penetrating through the first conductive layer below the first opening for exposing the bottom oxide layer, wherein the second cross-sectional width is smaller than the first cross-sectional width; and forming a memory layer on a sidewall of the first opening and filled in the second opening.

Abstract: A method for critical dimension control in which a substrate is received having an underlying layer and a patterned layer formed on the underlying layer, the patterned layer including radiation-sensitive material and a pattern of varying elevation with a first critical dimension. The method further includes applying an overcoat layer over the patterned layer, the overcoat layer containing a photo agent selected from a photosensitizer generator compound, a photosensitizer compound, a photoacid generator compound, a photoactive agent, an acid-containing compound, or a combination of two or more thereof. The overcoat layer is then exposed to electromagnetic radiation, wherein the dose of electromagnetic radiation applied to different regions of the substrate is varied, and then the overcoat layer and patterned layer are heated. The method further includes developing the overcoat layer and the patterned layer to alter the first critical dimension of the patterned layer to a second critical dimension.

Abstract: Provided is a crystalline multilayer structure having good semiconductor properties. The crystalline multilayer structure includes a base substrate and a corundum-structured crystalline oxide semiconductor thin film disposed directly on the base substrate or with another layer therebetween. The crystalline oxide semiconductor thin film is 0.1 ?m or less in a surface roughness (Ra).

Abstract: A method for manufacturing a light emitting element that includes preparing a wafer having a substrate and a semiconductor structure, the substrate including a plurality of protrusions at positions corresponding to lattice points on a regular triangular lattice. The method includes forming a plurality of first modified parts in the substrate by irradiating the substrate with a laser beam along first dividing lines, forming a plurality of second modified parts in the substrate by irradiating the substrate with a laser beam along second dividing lines, and dividing the wafer along the first modified parts and the second modified parts to obtain a plurality of light emitting elements.

Abstract: Provided is a sealing sheet capable of preventing void and filler segregation from occurring when forming a sealing body in which semiconductor chips are buried in the sealing sheet. The sealing sheet has a viscosity within the range of 1 Pa·s to 50000 Pa·s at 90° C.

Abstract: A method of forming a coating film includes horizontally supporting a substrate, supplying a coating solution to a central portion of the substrate and spreading the coating solution by a centrifugal force by rotating the substrate at a first rotational speed, decreasing a speed of the substrate from the first rotational speed toward a second rotational speed and rotating the substrate at the second rotational speed to make a surface of a liquid film of the coating solution even, supplying a gas to a surface of the substrate when the substrate is rotated at the second rotational speed to reduce fluidity of the coating solution, and drying the surface of the substrate by rotating the substrate at a third rotational speed faster than the second rotational speed.

Abstract: A gettering property evaluating method for a wafer includes: a gettering layer forming step of polishing a back surface opposite to a front surface of a semiconductor wafer by use of a polishing wheel to form polishing marks on the back surface and to form a gettering layer inside the semiconductor wafer and beneath the polishing marks; an imaging step of imaging at least a unit region of the back surface formed with the polishing marks by imaging means; a counting step of counting the number of the polishing marks having a width of 10 to 500 nm present in the unit region imaged; and a comparing step of comparing the number of the polishing marks counted by the counting step with a predetermined value to determine whether or not the counted number is not less than the predetermined value.

Abstract: The magnetic sensor includes a semiconductor substrate having Hall elements on a front surface of the semiconductor substrate, a conductive layer formed on a back surface of the semiconductor substrate, and a magnetic flux converging plate formed on the conductive layer. The magnetic flux converging plate is formed on the back surface of the semiconductor substrate through formation of the base conductive layer on the back surface of the semiconductor substrate, formation of a resist on the base conductive layer having an opening for forming the magnetic flux converging plate, formation of the magnetic flux converging plate in the opening of the resist by electroplating, removal of the resist, and removal of a part of the base conductive layer by etching with the magnetic flux converging plate as a mask.

Abstract: Provided here may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a first source seed layer, a second source seed layer disposed over the first source seed layer at a position spaced apart from the first source seed layer with a source area interposed between the first source seed layer and the second source seed layer, cell plugs configured to penetrate through the second source seed layer and extend into the source area, the cell plugs being disposed at positions spaced apart from the first source seed layer. The semiconductor device may also include an interlayer source layer configured to fill the source area.

Abstract: An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface provided with a bump and a second surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of adhering a protection tape having an adhesive layer to the first surface and embedding. The element chip manufacturing method includes a thinning process of grinding the second surface in a state where the protection tape is adhered to the first surface and thinning the substrate, after the bump embedding process, a mask forming process of forming a mask in the second surface and exposes the dividing regions, after the thinning process, a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape.

Abstract: A light emitting diode (LED) package includes a package body; an LED chip above the package body; a first wavelength conversion layer containing a first wavelength conversion material, and an upper surface portion covering a part of an upper surface of the LED chip and a lateral portion covering side surfaces of the LED chip; and a second wavelength conversion layer containing a second wavelength conversion material different from the first wavelength conversion material, and covering the first wavelength conversion layer and a remaining part of the upper surface of the LED chip.

Abstract: A semiconductor circuit comprises a Front End of Line (FEOL) comprising a plurality of transistors, each of which having a source region, a drain region and a gate region arranged between the source region and the drain region and comprising a gate electrode. The semiconductor circuit also comprises a buried interconnect that is arranged in the FEOL and electrically connected to the gate region from below through a bottom contact portion of the gate electrode. By using a buried interconnect the routing of the circuit may be facilitated.