Abstract: The invention features a method and a system for selecting a slot within a memory unit, e.g., cache, for removal. The memory unit is accessible to a plurality of processors, and each slot in the memory unit has a corresponding entry in an age table. Each time when a processor examines one of the entries, an age value of the entry is increased. When the age value is above a maturity age, the corresponding slot becomes a removable slot. Each processor also maintains statistics to estimate the number of removable slots in the memory unit. According to the statistics, adjusts a maturity age associated with the processor dynamically and independently to control the number of removable slots. Accordingly, the number removable slots can be maintained at a pre-determined percentage relative to the total number of slots in the memory unit.
Abstract: A system and apparatus for controlling a burst sequence in a synchronous memory is described. In one embodiment, the system comprises a synchronous memory and a burst read device coupled to the synchronous memory. In one embodiment, the burst read device is configured to sense a page of data as a current page from the synchronous memory, wherein the current page contains a fixed number of words of data. The device is further configured to latch the current page of data, and synchronously read the current page of data, one word at a time. In an alternate embodiment, the burst read device further comprises a wrap-bit. If the wrap-bit is not set, the burst read device is configured to latch the current page of data, adjust a word pointer to indicate a next word of data, and repeat latching and adjusting in a sequential burst read order.
Type:
Grant
Filed:
September 14, 1999
Date of Patent:
July 23, 2002
Assignee:
Intel Corporation
Inventors:
Terry L. Kendall, Kenneth G. McKee, Kishore Rao