Patents Examined by Boris Benenson
  • Patent number: 8854790
    Abstract: The present invention generally relates to an electrostatic chuck assembly for uniformly processing a wafer in a semiconductor wafer processing process, more particularly to prevent a byproduct formed from leakage of wafer processing materials from depositing between a wafer and the electrostatic chuck assembly. The electrostatic chuck assembly has a wafer holding member for holding a wafer; a shadow ring in engagement with the wafer holding member; and an insert ring disposed between the shadow ring and the wafer holding member. The wafer holding member has a wafer mounting surface and may preferably have a conical head having a tapered peripheral wall and a cylindrical portion. Alternatively, the wafer holding member is cylindrical and extends downwardly from the wafer mounting surface. The insert ring has an inner wall for sealably engaging the wafer holding member and preferably, is removable to allow for easy cleaning of the electrostatic chuck assembly.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventor: David Hsieh
  • Patent number: 7372686
    Abstract: A current detection unit samples motor current at every cycle corresponding to a cycle of the highest processing speed of a CPU. A current integral calculation unit integrates the value of the sampled motor current over a sampling period to calculate and output a current integral to an abnormality determination unit. The abnormality determination unit determines whether the current integral is larger than a threshold. When the abnormality determination unit determines that the current integral is larger than the threshold, it generates a detection signal indicating an abnormality in the motor current and outputs the signal to a relay drive unit and a notification unit. The relay drive unit receives the detection signal to generate a signal for turning off a system relay. The notification unit receives the detection signal to generate and output a signal to display means provided outside a power supply apparatus.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: May 13, 2008
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Kiyoe Ochiai
  • Patent number: 7372678
    Abstract: Resettable circuit interrupting devices having self-test and non-resettable or limited resettable power interrupting systems are provided. The permanent power interrupting system activates when a circuit interrupting device is no longer capable of operating in accordance with applicable standards governing such devices or the device is no longer capable of operating in accordance with its design characteristics.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: May 13, 2008
    Assignee: Leviton Manufacturing Co., Inc.
    Inventors: Nicholas L. DiSalvo, Ross Mernyk, Roger M. Bradley, Stephen Stewart, Frantz Germain, Armando Calixto
  • Patent number: 7372688
    Abstract: A differential mode surge protection apparatus includes first and second solid state protection devices in series between respective input and output connection points. The apparatus may be provided in conjunction with a common mode protection apparatus such as an isolation transformer. Alternatively, the apparatus may be provided integrated into a single miniaturized protection package. In a preferred embodiment, the apparatus includes a surge arrestor arranged to supplement protection conferred by the first and second solid state protection devices. The surge arrestor is capable of being triggered prior to breakdown of either the first or second solid state protection devices. The apparatus may be incorporated into digital processing cards such as LAN cards and also into cables to conveniently provide differential mode protection.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: May 13, 2008
    Assignee: FulTec Semiconductor, Inc.
    Inventor: Richard Harris
  • Patent number: 7365950
    Abstract: A wiring error detection circuit for providing the status of the wiring of an AC outlet and the status of the AC outlet's ground connection.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: April 29, 2008
    Assignee: TII Network Technologies, Inc.
    Inventor: Nisar A. Chaudhry
  • Patent number: 7355831
    Abstract: A fuel cell system or HVDC power source includes a fuel cell or DC power source having a high voltage direct current (HVDC) bus including y-capacitors, which connect the HVDC bus terminals to chassis or safety ground, and a fault current discharge compensation circuit interconnected with the HVDC bus. A monitoring circuit monitors a fault discharge current of the Y-cap circuit and generates a fault signal when the fault current occurs based on a rate of change of a voltage of the Y-cap circuit. A switching circuit redirects the majority of the fault discharge current.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: April 8, 2008
    Assignee: GM Global Technology Operations, Inc.
    Inventor: Stephen Raiser
  • Patent number: 7339774
    Abstract: A safety battery disconnect system for disconnecting a vehicle battery from the electrical system of the vehicle when an impact exceeding a predetermined magnitude is detected while maintaining electrical power input from the battery to selected portions of the vehicle electrical system. The system includes a shock sensor connected to a latching switch interposed between the battery and the vehicle fused electrical input system and is preferably a unitary unit mounted on or in close proximity to the battery.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: March 4, 2008
    Inventors: Peter M. Zdziech, John Richard Walls, III
  • Patent number: 7336460
    Abstract: A circuit of protection against electrostatic discharges, comprising a first MOS transistor for detecting a leakage current between a first input node of a circuit to be protected and a second node at an output voltage, a second MOS transistor constitute of a switch directly connecting said nodes, and a leakage current amplifier in the first transistor to control the second one.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: February 26, 2008
    Assignee: STMicroelectronics SA
    Inventors: Stéphanie Dournelle, Pascal Salome
  • Patent number: 7333312
    Abstract: An ESD device invention comprises first and second transistors formed in a substrate, each having a source, a drain and a gate, the source and drain of the first transaction being connected between ground and an I/O pin or input, the gate of the first transistor being connected to ground and the source and drain of the second transistor being connected between the substrate of the first transistor and the I/O pin or input; first and second capacitors connected in series between ground and the I/O pin or input; and at least a third transistor connected between ground and a node between the first and second capacitors to which the gate of the second transistor is also connected.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: February 19, 2008
    Assignee: Altera Corporation
    Inventors: Hugh Sungki O, Chih-Ching Shih, Cheng-Hsiung Huang, Yow-Juang Bill Liu
  • Patent number: 7333317
    Abstract: A portable ionizer is arranged for generating ionized air in an area of a user's fingers. The portable ionizer includes a battery-powered oscillator coupled via a high voltage conversion circuit to a positive electrode and a negative electrode for generating positive and negative ions. A fan positioned near the positive and negative electrodes is arranged providing a positive and negative ion flow path to the area of the user's fingers.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: February 19, 2008
    Assignee: International Business Machines Corporation
    Inventors: Susan Ann Hodapp Benysh, Edward Charles Gillard, Don Alan Gilliland, Dennis Elmer Maloney
  • Patent number: 7324316
    Abstract: A hot-swap circuit system for fan tray module includes a soft-start circuit module in charge of the power start of the fan tray module hot-plugged into an application system. The soft-start circuit module includes a capacitor and a field effect transistor. The capacitor discharges and the field effect transistor turns off when an input voltage is changed from a certain value to zero.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: January 29, 2008
    Assignee: Delta Electronics, Inc.
    Inventors: Hunter Chen, Chun-Lung Chiu, Wen-Shi Huang
  • Patent number: 7319579
    Abstract: A snubber circuit has a voltage detection circuit which detects that a voltage between first and second terminals exceeds a predetermined voltage, a protection circuit which performs control to prevent an overvoltage between the first and second terminals when the voltage detection circuit detects that the voltage between the first and second terminals exceeds the predetermined voltage, and a voltage control circuit which bypasses a portion of a main current flowing between the first and second terminals to the protection circuit when the voltage detection circuit detects that the voltage between the first and second terminals exceeds the predetermined voltage.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: January 15, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoki Inoue, Koichi Sugiyama
  • Patent number: 7319575
    Abstract: This invention provides a semiconductor device in which an ESD protection circuit and a termination circuit can be realized with a small die area. A PMOS transistor having an ESD protection function is placed between a signal node on a line from an signal terminal to an input buffer and a supply voltage node. Furthermore, a voltage generator circuit is placed to supply a reference voltage to the gate of the PMOS transistor. By the reference voltage controlled by the voltage generator circuit, a source drain resistance of the PMOS transistor is set. Thereby, the PMOS transistor can be made to function as a terminating resistor whose resistance can be set adaptively to a characteristic impedance of a transmission line, for example, connected to the signal terminal in addition to the ESD protection function.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: January 15, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Tatsuya Kawashimo, Hiroki Yamashita, Masayoshi Yagyu
  • Patent number: 7312967
    Abstract: By voltage limiting means, which provided in an IC as one of the components of an electronic apparatus, and a resistor, which is provided between a voltage input terminal of the IC and an external terminal of the electronic apparatus, an unexpected abnormal voltage generated in a DC power source such as an AC adaptor can be limited, and an overvoltage of not less than a predetermined value can be also prevented from being applied to the IC.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: December 25, 2007
    Assignee: Rohm Co., Ltd.
    Inventors: Kenichi Niiyama, Seiichi Yamamoto
  • Patent number: 7312973
    Abstract: An air conditioning apparatus incorporates an ion generating device that generates positive and negative ions by applying an alternating-current voltage between electrodes. The generated positive and negative ions coexist in the air and, when they attach to the surfaces of airborne bacteria, they react chemically with each other and generate radical hydroxyl and hydrogen peroxide, which extract hydrogen atoms from the cells of the bacteria and thereby kill them. This sterilizing effect is combined with the temperature-conditioning, dehumidifying, humidifying, air-purifying, and other functions of the air conditioning apparatus to bring about a comfortable and healthful indoor environment.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: December 25, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshinori Sekoguchi, Mamoru Morikawa
  • Patent number: 7312963
    Abstract: The present invention is directed to a protection device that includes line terminals coupled to a power source disposed in an electric power distribution system. The protection device is configured to protect a portion of the power distribution system from at least one fault condition. The device includes a receptacle member that has includes a housing and a cover. The cover includes receptacle openings configured to accommodate plug contact blades. Receptacle contacts are disposed in the housing. The receptacle contacts are also coupled to the line terminals to thereby establish an electrical connection between the receptacle contacts and the line terminals. Each receptacle contact is in communication with a corresponding receptacle opening. A protective shutter mechanism is integrated into the housing. The protective shutter mechanism is movable from a closed position to an open position upon insertion of the plug contact blades.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: December 25, 2007
    Assignee: Pass & Seymour, Inc.
    Inventors: Dejan Radosavljevic, Richard Weeks
  • Patent number: 7301743
    Abstract: A two channel universal device for advanced protection from a short circuit current which evaluates a rate-of-change of current in a supply feeder and compares the current in the supply feeder and the current in load phases generating a differential signal in such a way that in normal conditions, when the load is running or starting, the differential signal is virtually zero. The differential signal and the rate-of-change of current in the supply feeder are compared with the settings of the protective device. If both the value of the rate-of-change of current and the value of the differential signal simultaneously exceed their settings, after an adjustable time delay, the device produces a signal to open the circuit. The existence of two conditions necessary to initiate the trip signal to cause the circuit to open ensures the reliable operation of this device and provides a feasible fast protection scheme.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: November 27, 2007
    Inventors: Vassili Rozine, Max H. Adams
  • Patent number: 7301739
    Abstract: A ground-fault circuit-interrupter method and system for three-phase electrical power systems including a plurality of GFCI units and a processor forming a ground-fault circuit interrupting system for use in a three-phase power distribution network including a three-phase source of electrical power, a three- or four-wire main circuit, and a plurality of three- or four-wire feeder circuits connected across the main circuit. A GFCI unit is provided in the main circuit and in each of the feeder circuits. The processor is programmed to continuously monitor the main GFCI unit and each feeder GFCI unit to determine when and where a fault has occurred and, in response thereto, to interrupt the faulted circuit and to inhibit tripping of the non-faulted circuits. The novel GFCI system is applicable for solidly-grounded, resistance-grounded, or ungrounded as well as other three-phase systems.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: November 27, 2007
    Assignee: Chevron U.S.A. Inc.
    Inventor: Paul S. Hamer
  • Patent number: 7301740
    Abstract: The present invention is to provide an improved surge protector device. The present invention's surge protector device basically has a plurality of metal bars which are combined to a single body by a continuous high-resistive film of semiconductor crystal so that there is no gap between adjacent metal bars; and electrodes formed on the endmembers of the said metal bars composing the single body. Thus, the present invention's surge protector device is fabricated so as to have no air gap between adjacent ones of the metal bars. As a result, the present invention's protector device can operate in such a way that the surge protector device changes from a non-conductive state to a conductive state due to breakdown in depletion region accompanying the semiconductor crystal when the voltage across the electrodes exceeds a threshold voltage because of a surge.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: November 27, 2007
    Inventor: Takashi Katoda
  • Patent number: 7301746
    Abstract: A thermal shutdown circuit for protecting a main FET that conducts a load current ILOAD. A reference circuit provides a temperature current proportional to temperature. A thermal sensor circuit has a resistor and generates an output signal signaling thermal shutdown when the voltage generated across the resistor by the temperature current exceeds a predetermined value. A sense FET having a size smaller than the main FET conducts a sense current ISENSE proportionately smaller than ILOAD. A current mirror mirrors a scaled current proportional to ISENSE to be conducted through the resistor, the scaled current being scaled so as to cause the voltage generated across the resistor to exceed the predetermined value when ILOAD exceeds a predetermined value.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: November 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Vijayalakshmi Devarajan, John H. Carpenter, Jr., Benjamin Lee Amey