Abstract: The present disclosure provides a method for preparing a semiconductor structure using the hardmask structure. The method includes forming a conductive layer on a substrate; forming a first ashable hardmask layer on the conductive layer; forming a first anti-reflection coating on the first ashable hardmask layer; forming a second ashable hardmask layer on the first anti-reflection coating, wherein a modulus of the first ashable hardmask layer is greater than a modulus of the second ashable hardmask layer; etching the first ashable hardmask layer, the first anti-reflection coating, and the second ashable hardmask layer to transfer a first pattern to at least the first ashable hardmask layer; and etching the conductive layer according to the first ashable hardmask layer to form a patterned conductive layer.

Abstract: An Ill-nitride semiconductor based heterojunction power device is disclosed and includes a first and second heterojunction transistors formed on a substrate. The first and second heterojunction transistors include first and second Ill-nitride semiconductor regions formed over the substrate. The first Ill-nitride semiconductor region includes a first heterojunction, a first terminal connected to the first Ill-nitride semiconductor region, a second terminal laterally spaced from the first terminal and connected to the first Ill-nitride semiconductor region, and a first gate region over the first Ill-nitride semiconductor region between the first and second terminals.

Abstract: A display device includes a substrate, an organic insulating layer over the substrate, a metal layer over the organic insulating layer, and a light emitting element over the metal layer. The organic insulating layer includes a convex portion that overlaps the light emitting element. The metal layer covers the convex portion and includes a step portion along a side surface of the convex portion.

Abstract: A display motherboard and a manufacturing method of a display substrate are provided. The display motherboard includes: a substrate including a valid area and an edge area, the valid area including a plurality of panel areas and a to-be-cut area, and the panel area including a display area and a frame area; multiple first power lines in each display area and the edge area and extending along a first direction; multiple first display electrodes in each display area and multiple virtual electrodes in the edge area, the first display electrodes and the virtual electrodes being in the same layer; wherein an orthographic projection of each first display electrode on the substrate overlaps an orthographic projection of at most one first power line on the substrate, and an orthographic projection of each virtual electrode on the substrate overlaps orthographic projections of at least two first power lines on the substrate.

Abstract: A microdisplay comprising a light emitting OLED stack on top of a silicon-based backplane with individually addressable pixels and control circuitry wherein the light emitting OLED stack has three or more OLED units between a top electrode and a bottom electrode; and the control circuitry of the silicon-based backplane comprises at least two transistors with their channels connected in series between an external power source VDD, and the bottom electrode of the OLED stack. The light-emitting OLED stack preferably has a Vth of at least 7.5V or more. The control circuit can include a protection circuit comprised of a p-n diode, preferably a bipolar junction transistor.

Abstract: An image display element includes pixels, a driving circuit substrate, a microlens, and an inter-pixel partition. The pixels are disposed in an array, each including a micro light emitting element. The driving circuit substrate includes a driving circuit configured to supply a current to the micro light emitting element and cause the micro light emitting element to emit light. The microlens is disposed for each of the pixels. The inter-pixel partition is disposed between the pixels and extends from a light emitting surface of the micro light emitting element to the microlens.

Abstract: According to an aspect of the present disclosure, an organic light emitting display apparatus includes an organic light emitting diode; a driving transistor which supplies a driving current to the organic light emitting diode; and a plurality of switching transistors to transmit a reference voltage and a data voltage to a gate electrode of the driving transistor, respectively. According to the present disclosure, one frame is divided into a refresh period in which a data voltage is written and a hold period in which the data voltage written in the refresh period is held. The refresh period includes an initialization period, a sampling period, a programming period, and an emission period, and the sampling period and the programming period may be separate from each other.

Abstract: A display comprising a light emitting OLED stack on top of a silicon-based backplane with individually addressable pixels and control circuitry wherein the control circuitry of the silicon-based backplane comprises at least one driving transistor where a first terminal of the driving transistor is electrically connected to an external power source VDD, and the second terminal of the driving transistor is electrically connected to the bottom electrode of the OLED stack; wherein the gate of the driving transistor is controlled by a data signal which supplied by a scan transistor controlled by a signal from select line SELECT1; and the control circuitry additionally comprises a protection circuit comprising a bipolar junction transistor. There can be a switch transistor between the scan transistor and the gate of the driving transistor for microdisplay applications. The OLED stack can comprise two or more OLED light-emitting units.

Abstract: The present disclosure relates to an organic light-emitting diode display device that comprises a first substrate on which first, second and third subpixels each including an emission area and a non-emission area are defined; first, second and third light-emitting diodes disposed in the first, second and third subpixels on the first substrate, respectively; a second substrate over the first, second and third light-emitting diodes; and a scattering pattern corresponding to the first subpixel and disposed over the first light-emitting diode or under the first substrate, wherein the first subpixel has an area reflectance higher than the second and third subpixels.

Abstract: Provided are a display panel and a display device. The display panel includes a substrate, a light-emitting element located on a side of the substrate, and a deformation module located between the substrate and the light-emitting element and including at least one deformation element. In a direction perpendicular to a plane where the substrate is located, the at least one deformation element in the deformation module overlaps the light-emitting element. Provided are a display panel and a display device to change a light-emitting angle of a light-emitting element, so that users can obtain a better view angle and the display effect can be improved.

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and memory opening fill structures including vertical stacks of memory elements are formed through the vertically alternating sequence. Backside trenches are formed to divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers. Bridge structures are formed within each of the backside trenches. The sacrificial material layers are replaced with electrically conductive layers while the bridge structure are present within the backside trenches.

Abstract: A conductive structure includes: a conductive pillar and at least one embedded block arranged in the conductive pillar, a coefficient of thermal expansion of the embedded block being less than that of the conductive pillar. When the conductive pillar is heated and expanded, an extrusion effect of the conductive pillar on a structure adjacent to the conductive pillar can be reduced, thereby improving the performance of the semiconductor structure.

Abstract: The present disclosure provides a display panel including: a substrate and a cover plate, disposed oppositely; a plurality of drive transistors, a plurality of reading transistors and a plurality of Schottky photodiodes, which are disposed on the substrate and located at a side of the substrate facing toward the cover plate; each of the Schottky photodiodes includes a photosensitive active layer and an interdigital electrode layer, the interdigital electrode layer is disposed on the photosensitive active layer and includes at least one first interdigital electrode and at least one second interdigital electrode spaced apart, each of the at least one first interdigital electrode is connected to a corresponding one of the reading transistors, and each of the at least one second interdigital electrode is connected to a bias signal terminal; a plurality of light-emitting units, disposed between the substrate and the cover plate and connected to the drive transistors one-to-one.

Abstract: A method includes forming a dielectric layer over a substrate; forming a patterned amorphous silicon layer over a dielectric layer; depositing a first spacer layer over the patterned amorphous silicon layer; depositing a second spacer layer over the first spacer layer; forming a photoresist having an opening over the substrate; depositing a hard mask layer in the opening of the photoresist; after depositing the hard mask layer in the opening of the photoresist, removing the photoresist; and performing an etching process to etch the dielectric layer by using the patterned amorphous silicon layer, the first spacer layer, the second spacer layer, and the hard mask layer as an etch mask, in which the etching process etches the second spacer layer at a slower etch rate than etching the first spacer layer.

Abstract: A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed. The method of manufacturing a semiconductor structure includes: providing a substrate, and forming a first sacrificial layer on the substrate, where the first sacrificial layer includes a first sacrificial dielectric layer and a second sacrificial dielectric layer; patterning the first sacrificial layer, and forming first intermediate pattern structures that are arranged at intervals, where a first gap is provided between two adjacent first intermediate pattern structures; forming a first spacer pad layer in the first gap, where the first spacer pad layer covers sidewalls of each of the two adjacent first intermediate pattern structures and a bottom of the first gap; removing the first spacer pad layer at the bottom of the first gap, and the second sacrificial dielectric layer; and removing the first sacrificial dielectric layer, to form first pattern structures.

Abstract: A memory device and method of making the same is provided. The memory device includes a first electrode, an oxygen scavenging layer on the first electrode, a hard mask on the oxygen scavenging layer, and a second electrode on the hard mask. A switching layer is arranged on a portion of the oxygen scavenging layer, and the switching layer is conformal to a side surface of the hard mask.

Abstract: Embodiments of the present disclosure provide a forming method of a semiconductor structure and a semiconductor structure. The forming method includes: providing a base, the base includes a central region and dummy regions, and the central region includes a molding region and cutting regions; forming multiple spaced core pillars on the base; forming an initial mask layer surrounding and covering a sidewall of each core pillar on the base; removing the initial mask layers located in each cutting region to form multiple spaced mask sidewall strips in the molding region, and retaining at least one of the initial mask layers in each dummy region as a ring-shaped sidewall; removing the core pillars located in the central region and the dummy regions; and etching the base to form multiple functional structures, and etching the base to form dummy functional structures on two sides of the multiple functional structures.

Abstract: A method of fabricating an air gap includes receiving a first thickness information of an inter-metal dielectric layer formed on a substrate and receiving a second thickness information of an inter-layer dielectric layer formed on the substrate. Then, a first etching is performed, wherein the first etching includes etch the inter-metal dielectric layer based on a first etching control value corresponding to the first thickness information. After the first etching, a second etching is performed to etch the inter-layer dielectric layer based on a second etching control value corresponding to the second thickness information.

Abstract: A display transferring structure includes a transfer substrate including a plurality of recesses, each of the plurality of recesses including a first trap having a space in which a predetermined object can be moved and a second trap connected to the first trap and having a shape and size in which the object can be seated; and a micro-semiconductor chip positioned in the second trap. The micro-semiconductor chip may be self-aligned in a correct position by the display transferring structure.

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and memory opening fill structures including vertical stacks of memory elements are formed through the vertically alternating sequence. Backside trenches are formed to divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers. A set of one or more bridge structures including a doped semiconductor material is formed within each of the backside trenches. The sacrificial material layers are replaced with electrically conductive layers while the sets of at least one bridge structure are present within the backside trenches.