Abstract: A display transferring structure includes a transfer substrate including a plurality of recesses, each of the plurality of recesses including a first trap having a space in which a predetermined object can be moved and a second trap connected to the first trap and having a shape and size in which the object can be seated; and a micro-semiconductor chip positioned in the second trap. The micro-semiconductor chip may be self-aligned in a correct position by the display transferring structure.

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and memory opening fill structures including vertical stacks of memory elements are formed through the vertically alternating sequence. Backside trenches are formed to divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers. A set of one or more bridge structures including a doped semiconductor material is formed within each of the backside trenches. The sacrificial material layers are replaced with electrically conductive layers while the sets of at least one bridge structure are present within the backside trenches.

Abstract: Embodiments of the present disclosure relates to method of forming trench and via features using dielectric and metal mask layers. Particularly, embodiments of present disclosure provide a hard mask stack including a first dielectric mask layer, and second dielectric mask layer and a metal mask layer, wherein the first dielectric mask layer and second dielectric mask layer have a high etch selectivity.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line, an oxide semiconductor (OS) layer contacting a source line and a bit line, and a conductive feature interposed between the memory film and the OS layer. The memory film is disposed between the OS layer and the word line. A dielectric material covers sidewalls of the source line, the memory film, and the OS layer.

Abstract: Disclosed are an active region, an active region array and a formation method thereof. The active region is formed in a substrate. The active region is provided with a wordline structure. The wordline structure penetrates the active region in a first direction and divides the active region into a source region and a drain region. The source region and the drain region are arranged in a second direction, and a size of the drain region in a third direction is greater than that of the source region in the third direction. An angle between the first direction and the second direction is an acute angle, and the third direction is perpendicular to the second direction.

Abstract: The present disclosure relates to a solid-state imaging element and an electronic device capable of increasing the capacitance of a charge holding unit. The solid-state imaging element includes a pixel including a photodiode, an FD that accumulates charges generated in the photodiode, and a charge holding unit that is connected in parallel with the FD. The charge holding unit includes a wiring capacitance formed by parallel running of a first wiring connected to a first potential and a second wiring connected to a second potential different from the first potential. The present disclosure can be applied to a solid-state imaging element that performs global shutter type imaging.

Abstract: Some examples of this disclosure relate to the field of the semiconductor technology, and disclose a method for manufacturing a semiconductor structure. The method for manufacturing of the semiconductor structure includes: providing a base, wherein the base includes a metal layer and an oxide located in the metal layer or on a surface of the metal layer; and performing heat treatment on the base, wherein a reducing gas is introduced during the heat treatment, and the metal layer is converted into a metal compound layer after the heat treatment. This disclosure can improve the performance of the semiconductor structure.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. The channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. A wall in the lowest conductive tier is aside the conducting material. The wall is in a region that is edge-of-plane relative to the memory plane. The edge-of-plane region comprises a TAV region. The wall is horizontally-elongated relative to an edge of the TAV region that is in the edge-of-plane region.

Abstract: A semiconductor structure and its manufacturing method are provided. The method includes sequentially forming an insulating layer and a patterned mask layer on a substrate. The patterned cover curtain layer has an opening, and the opening includes a main body portion and two extension portions located at both ends of the main body portion. The method includes sequentially forming a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer on the insulating layer. The first sacrificial layer fills the extension portions and defines a recess in the main body portion. The second sacrificial layer is formed in the recess defined by the first sacrificial layer. The third sacrificial layer is formed on the first sacrificial layer located in the extension portions.

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a plurality of first energy-sensitive patterns over the target layer. The method also includes forming a lining layer conformally covering the first energy-sensitive patterns. A first opening is formed over the lining layer and between the first energy-sensitive patterns. The method further includes filling the first opening with a second energy-sensitive pattern, and performing an etching process to form a plurality of second openings and a third opening in the target layer, wherein the third opening is between the second openings, and the second openings and the third opening have different depths.