Abstract: A method of planarizing a layer of an integrated circuit. In one embodiment, a liquid film is applied over the layer, using extrusion coating techniques. In another embodiment, the layer itself may be applied as a liquid film, using extrusion techniques.

Abstract: An array apparatus has a micromachined SOI structure, such as a MEMS array, mounted directly on a class of insulative substrate, such as low temperature co-fired ceramic or a thermal-coefficient of expansion matched glass, in which is embedded electrostatic electrodes disposed in alignment with the individual MEMS elements, where the electrostatic electrodes are configured for substantial fanout. In a specific embodiment in order to compensate for differences in thermal-expansion characteristics between SOI and ceramic, a flexible mounting is effected by means of posts, bridges and/or mechanical elements which allow uneven expansion in x and y while maintaining z-axis stability. Methods according to the invention include fabrication steps wherein electrodes are fabricated to a post-fired ceramic substrate and coupled via traces through the ceramic substrate to driver modules.

Abstract: Provided is an MOS transistor capable of reducing gate overlap capacitance without decreasing the driving current of the MOS transistor. Specifically, a double-angle smile oxidation structure is obtainable by curving the side surface of a gate electrode (22) so as to widen upwardly, and thickening the edge portion of a gate oxide film (21) by re-oxidation. The impurity concentration of a source/drain layer under the double-angle smile oxidation structure (a region around point B) is set to the range of 4×1018 cm?3±40%.

Abstract: The memory cell transistor includes, in a first well region, a pair of memory electrodes, one of which serves as source electrode and the other serves as a drain electrode and a channel region interposed between the pair of memory electrodes. There is, on a channel region, a first gate electrode disposed near its corresponding memory electrode with an insulating film interposed therebetween, and a second gate electrode disposed through insulating films and a charge storage region and electrically isolated from the first gate electrode. A first negative voltage is applied to the first well region to form a state of a reverse bias greater than or equal to a junction withstand voltage between the second gate electrode and the memory electrode near the second gate electrode, thereby enabling injection of hot electrons into the charge storage region and injection of electrons from the well region to the charge storage region.

Abstract: Methods for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example, a via lined with an insulative material may be filled with a material such as copper to create an insulated conductive via through the substrate.

Abstract: A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.

Abstract: A cell transistor includes source/drain regions formed at a lower level than part of its channel region. A select transistor has a channel region and source/drain regions formed at substantially the same level as the source/drain regions of the cell transistor. One of the source/drain regions of the cell transistor and one of the source/drain regions of the select transistor are electrically interconnected to each other in substantially the same plane.

Abstract: A chemical vapor deposition method includes providing a semiconductor substrate within a chemical vapor deposition chamber. At least one liquid deposition precursor is vaporized with a vaporizer to form a flowing vaporized precursor stream. The flowing vaporized precursor stream is initially bypassed from entering the chamber for a first period of time while the substrate is in the deposition chamber. After the first period of time, the flowing vaporized precursor stream is directed to flow into the chamber with the substrate therein under conditions effective to chemical vapor deposit a layer over the substrate. A method of etching a contact opening over a node location on a semiconductor substrate is disclosed.

Abstract: A method of producing a semiconductor device capable of suppressing damages by corrosion on wiring in a catalyst process performed in electroless plating processing on a Co base material, etc. in producing a semiconductor device having wiring of Cu, etc., having steps of forming metal wiring including an additive on a first insulation film formed in a semiconductor substrate, and forming on the metal wiring a barrier layer for preventing diffusion of constituting elements of the metal wiring, wherein said additive is an element to reduce corrosion of the metal wiring at the time of forming the barrier layer in the step of forming the metal wiring.

Abstract: A magnetic memory device includes a first wiring layer which runs in the first direction, a memory element which is arranged above the first wiring layer, second wiring layers which are arranged on the memory element and run in a second direction different from the first direction, and a first magnetic shield layer which is formed on the side surface of each second wiring layer and formed around the side surface of the memory element.

Abstract: A current reference, which may be fabricated independently, on a die, as part of an integrated circuit, or a system, or in various other forms, is disclosed. The current reference may include a voltage source having a substantially temperature stable output voltage, a first semiconductor device biased by the substantially temperature stable output voltage to provide a first output current, and a second semiconductor device providing a second output current, wherein a reference current is provided approximately equal to the difference between the first and second output currents.

Abstract: The invention provides a semiconductor device having less defectives in shape of a patterned wiring layer even in a case of having a wiring layer for which patterning is required to be carried out over a longer period of etching time, and a method for producing the same. By carrying out dry etching using a fluorine-based gas with a photoresist 17a used as a mask, an auxiliary mask 15a is formed by patterning the insulation membrane. Next, by carrying out dry etching using a chlorine-based gas using the auxiliary mask 15a and the remaining photoresist 17a as masks, wiring 13a is formed by patterning the wiring layer 13. In the second etching, the auxiliary mask 15a is scarcely etched. Therefore, if the thickness of the photoresist 17a is equivalent to that in the prior arts, it is possible to pattern a thicker wiring layer 13 than in the prior arts.

Abstract: A copackaged electronic device comprises a diode device having an anode coupled to a drain electrode of a switching device and a cathode capable of being coupled to an external circuit. The switching device may be controlled by an integrated circuit mounted on a source electrode of the switching device and electrically connected such that the integrated circuit is capable of controlling switching of the switching device. For example, the device is used in a power factor correction circuit. The diode device comprises at least one inverted diode having a solderable anode and a wire-bondable cathode.

Abstract: One embodiment of the present invention provides a system for co-fabricating strained and relaxed crystalline, poly-crystalline, and amorphous structures in an integrated circuit device using common fabrication steps. The system operates by first receiving a substrate. The system then fabricates multiple layers on this substrate. A layer within these multiple layers includes both strained structures and relaxed structures. These strained structures and relaxed structures are fabricated simultaneously using common fabrication steps.

Abstract: A manufacturing method for a crystalline semiconductor material including a plurality of semiconductor crystal grains is provided. The manufacturing method includes forming an amorphous or polycrystalline semiconductor layer on a substrate having a flat surface; forming a plurality of projections each having a side wall surface substantially perpendicular to the flat surface of the substrate, a height set in the range of about 1 nm to less than or equal to about ¼ of the thickness of the semiconductor layer, and a lateral dimension set in the range of about 3 ?m to about 18 ?m in a direction parallel to the flat surface of the substrate; and heating the semiconductor layer a number of times by using a pulsed laser thereby forming the crystalline semiconductor material including the crystal grains each having a specific plane orientation with respect to a direction perpendicular to the flat surface of the substrate so that the crystal grains respectively correspond to the projections.

Abstract: A memory cell and method for controlling the resistance properties in a memory material are provided. The method comprises: forming manganite; annealing the manganite in an oxygen atmosphere; controlling the oxygen content in the manganite in response to the annealing; and, controlling resistance through the manganite in response to the oxygen content. The manganite is perovskite-type manganese oxides with the general formula RE1-xAExMnOy, where RE is a rare earth ion and AE is an alkaline-earth ion, with x in the range between 0.1 and 0.5. Controlling the oxygen content in the manganite includes forming an oxygen-rich RE1-xAExMnOy region where y is greater than 3. A low resistance results in the oxygen-rich manganite region. When y is less than 3, a high resistance is formed. More specifically, the process forms a low resistance oxygen-rich manganite region adjacent an oxygen-deficient high resistance manganite region.

Abstract: A semiconductor package production method containing a step in which a bond layer made of a single-layer film thermoset bond is provided on the back of a wafer on which many semiconductor devices are formed, a dicing tape is pasted onto its bond layer side, and the bond layer and the wafer are diced simultaneously in order to obtain semiconductor devices with the bond layer, and a step in which the semiconductor devices with the bond layer are detached from the dicing tape and die-attached to interposing substrates serving as bodies to which they are bonded; wherein, the aforementioned film thermoset bond contains an epoxy resin, an epoxy resin hardener, and a phenoxy resin as well as 50-80 wt % of spherical silica, and the bond layer is 100 ?m or thicker. A semiconductor device made by this method and a wafer for use with this method.

Abstract: The major surface of a semiconductor substrate of a semiconductor device includes first and second regions and a boundary area therebetween. A first gate insulating film and a first gate electrode are formed in the first region. A second gate insulating film different from the first gate insulating film and a second gate electrode are formed in the second region. A device isolation region is formed in the boundary area. This device isolation region includes a trench formed in the major surface, and an insulating layer having a portion buried in the trench and a portion projecting upward from the major surface. The bottom of the trench has depths different with portions.

Abstract: A semiconductor wafer cleaning formulation, including 1-21% wt. fluoride source, 20-55% wt. organic amine(s), 0.5-40% wt. nitrogenous component, e.g., a nitrogen-containing carboxylic acid or an imine, 23-50% wt. water, and 0-21% wt. metal chelating agent(s). The formulations are useful to remove residue from wafers following a resist plasma ashing step, such as inorganic residue from semiconductor wafers containing delicate copper interconnecting structures.

Abstract: A method of forming an aligned dual damascene opening, comprising including the following sequential steps. A layer stack is formed over the metal structure. The layer stack comprises, in ascending order: a bottom etch stop layer; a lower dielectric material layer; a middle etch stop layer; a middle dielectric material layer; and an upper dielectric layer. A patterned mask layer is formed over the patterned upper dielectric layer leaving exposed opposing portions of the patterned upper dielectric layer. The middle dielectric material layer is patterned to form an opening therein using the patterned mask layer and the exposed portions of the upper dielectric layer as masks.