Abstract: A field effect transistor having a quantum-wave interference layer with plural periods of a pair of a first layer W and a second layer B. The second layer B has wider band gap than the first layer W, and the quantum-wave interference layer is formed in a region adjacent to a channel. Each thickness of the first layer W and the second layer B is determined by multiplying by an odd number one fourth of quantum-wave wavelength of carriers in each of the first layer W and the second layer B, which exist around the lowest energy level of the second layer B. The quantum-wave interference layer functions as a carrier reflecting layer, and enable to prevent leakage current from a source to a region except a drain.

Abstract: The potential on a pixel cell having a gated diode and a read out transistor is set to an initial level prior to an image integration period. During the image integration period, absorbed photons cause the potential on the pixel cell to change. After the image integration period, the pixel cell is then reset and read out by applying a number of pulses to the gated diode. Each of the pulses causes a fixed amount of charge to be injected into the cell. When the potential on the cell has again returned to the initial level, the number of absorbed photons is determined by counting the number of pulses that were required to return the potential to the initial level. The read out transistor is used to determine when the potential is at the initial level by biasing the transistor to output a current that corresponds to the potential on the pixel cell.

Abstract: According to the invention, a bidirectional semiconductor light emitting element is provided, which comprises: a first semiconductor region of a first type of conductivity; a second semiconductor region of a second type of conductivity provided on the first semiconductor region; a third semiconductor region of a first conductivity type provided on the second semiconductor region; and a semiconductor light emitting layer interposed in the second semiconductor region, the light emitting layer emitting light by an injection of a tunneling current generated at a reverse-biased p-n junction between the first and second regions or between the second and third regions under an application of a voltage of a first polarity across the first and third semiconductor regions, and the light emitting layer emitting light by an injection of a tunneling current generated at another reverse-biased p-n junction between the first and second regions or between the second and third regions under an application of a voltage of a se

Abstract: Provided is a method and apparatus for the production of a semiconductor device, the method and the apparatus producing a high quality and highly functional semiconductor device efficiently at low temperatures in a short time and also a high quality and highly functional semiconductor device produced by the method and apparatus. The semiconductor device is produced by forming a film of a nitride compound on a substrate having heat resistance at 600° C. or less, wherein the nitride compound includes one or more elements selected from group IIIA elements of the periodic table and a nitrogen atom and produces photoluminescence at the band edges at room temperature.

Abstract: An array of nanowires having a relatively constant diameter and techniques and apparatus for fabrication thereof are described. In one embodiment, a technique for melting a material under vacuum and followed by pressure injection of the molten material into the pores of a porous substrate produces continuous nanowires. In another embodiment, a technique to systematically change the channel diameter and channel packing density of an anodic alumina substrate includes the steps of anodizing an aluminum substrate with an electrolyte to provide an anodic aluminum oxide film having a pore with a wall surface composition which is different than aluminum oxide and etching the pore wall surface with an acid to affect at least one of the surface properties of the pore wall and the pore wall composition.

Abstract: In a method of fabricating a COB DRAM cell, a polysilicon plug is formed on the source and drain in self-alignment with the gate electrode. A bit line contact and a storage electrode contact are formed on the polysilicon plug thereby to reduce the aspect ratio of both the bit line contact and the storage electrode contact. With the polysilicon plug formed in self-alignment with the gate electrode, short-circuiting of contacts of adjacent element regions and short-circuiting of the plugs of the source and drain will not occur, leading to high protection against misregistration. Moreover, an independent lithography process is not required for forming the polysilicon plug, and, therefore, the number of fabrication steps is reduced.

Abstract: A practical operational amplifier circuit is formed using thin film transistors. An operational amplifier circuit is formed by thin film transistors formed on a quartz substrate wherein 90% or more of n-channel type thin film transistors have mobility at a value of 260 cm2/Vs or more and wherein 90% or more of p-channel type thin film transistors have mobility at a value of 150 cm2/Vs or more. The thin film transistors have active layers formed using a crystalline silicon film fabricated using a metal element that promoted crystallization of silicon. The crystalline silicon film is a collection of a multiplicity of elongate crystal structures extending in a certain direction, and the above-described characteristics can be achieved by matching the extending direction and the moving direction of carriers.

Abstract: A semiconductor light emitting device includes: a substrate; a contact layer made of a gallium nitride based compound semiconductor formed on the substrate; a stripe-shaped conductive selective growth mask formed above the contact layer; and a layered structure made of a gallium nitride based compound semiconductor. The layered structure includes at least a pair of cladding layers, formed on the conductive selective growth mask, and an active layer, including at least one layer, sandwiched by the cladding layers.

Abstract: The invention relates to an erasable non-volatile memory in which a diode is formed at each point of intersection between the x-selection lines (Ki) and y-selection lines (Rj), of which diode the anode and cathode are conductively connected to the x- and y-selection lines. The diodes are formed in hydrogenated amorphous silicon or silicon compounds such as amorphous Si−xGex. Writing takes place by means of a current pulse through selected diodes. The current in the forward direction becomes much lower, for example a few hundred times lower, than in diodes which are not selected, probably owing to degradation in the semiconductor material. The diodes may be returned to their original state again (i.e. be erased) through heating, for example at a temperature of 200° C. during 100 minutes. Preferably, the diodes are formed by Schottky diodes because the characteristic in the reverse direction does not (substantially) change in this type of diode.

Abstract: The present invention provides a semiconductor light-emitting device including a first clad layer comprising a first conductive type of AlGaAsP compound, a second clad layer that is located next to the first clad layer, comprises a first conductive type of AlGaInP compound and has a thickness of up to 0.5 &mgr;m, an active layer that is located next to the second clad layer and comprises a first or second conductive type AlGaInP or GaInP, a third clad layer that is located next to the active layer, comprises a second conductive type of AlGaInP compound and has a thickness of up to 0.5 &mgr;m, and a fourth clad layer that is located next to the third clad layer and comprises a second conductive type of AlGaAsP compound, and/or a light-extracting layer that comprises a second conductive type AlGaP or GaP and has a thickness of 1 &mgr;m to 100 &mgr;m.

Abstract: In an electron emission element having an emitter section for emitting electrons, the emitter section includes, on a first conductive electrode, a structure in which at least a first semiconductor layer, a second semiconductor layer, an insulating layer and a second conductive electrode are deposited sequentially; and the first and second semiconductor layers include at least one of carbon, silicon and germanium as a main component, and the first semiconductor layer includes at least one type of atoms among carbon atom, oxygen atoms and nitrogen atoms which is different from the main component.

Abstract: A semiconductor device and fabrication process are provided in which a patterned metal layer is formed over a polysilicon line. The polysilicon line is disposed on a substrate and may, for example, be a gate electrode. A dielectric layer is disposed adjacent the polysilicon line and the patterned metal layer is formed over the polysilicon line. The device may further include a second polysilicon line, such as a gate electrode, and the patterned metal layer may extend over the top of the second polysilicon line and interconnect the two polysilicon lines. A contact for the polysilicon line is coupled to the patterned metal layer. The use of a patterned metal line may provide a larger footprint for the contact then the underlying polysilicon line(s) and may decrease the sheet resistance to the polysilicon line(s).

Abstract: An integrated circuit structure is provided with a local interconnect layer and a first metal interconnect layer which are both capable of bridging over underlying conductive regions. The structure comprises a first dielectric layer formed to a height or thickness equal to or preferably exceeding the height of the highest conductive regions of the underlying integrated circuit devices; a second dielectric layer formed above the first dielectric layer; one or more local interconnects formed in the second dielectric layer; and a thin third dielectric layer formed over the second dielectric layer and the local interconnects therein. The thin third dielectric layer has a thickness not exceeding about 2000 Å, and preferably ranging from about 1000 Å to about 1500 Å. A first layer of metal interconnects is formed over the thin third dielectric layer.

Abstract: Any oxide superconductor Josephson junction element having an oxide superconductor oriented in the c-axis direction with respect to a substrate, and a needle-like, a-axis (or b-axis) oriented oxide superconductor. Both sides of the needle-like, a-axis (or b-axis) oriented oxide superconductor are sandwiched between the c-axis oriented superconductors. The crystal boundary sections between the needle-like, a-axis (or b-axis) oriented oxide superconductor and each of the c-axis oriented superconductors form a weak link of the Josephson junction. The needle-like, a-axis (or b-axis) oriented oxide superconductor is grown such that the c-axis direction thereof is oriented in the (110) direction which is inclined at an angle of 45 degrees with respect to the (100) direction or (010) direction of the c-axis oriented superconductors.

Abstract: A piezoelectric device is manufactured by: (1) mirror finishing surfaces of a first substrate and a second substrate made of a piezoelectric element; (2) forming grooves on at least one of the two surfaces of the first and second substrates; (3) joining the mirror-finished surfaces of the first substrate and the second substrate; (4) applying heat to the joined substrates and bonding them; (5) forming an opening on the first substrate so that a part of the exposed areas of the second substrate is exposed through the opening; (6) forming piezoelectric devices by forming electrodes on at least one of the second substrate through the opening and a corresponding area to the exposed area on the rear side of the second substrate; and (7) dividing the bonded substrates into portions each having one of the piezoelectric devices. Through this manufacturing method, piezoelectric devices with high yield ratios and high reliability can be obtained.

Abstract: A Plastic Ball Grid Array electronic package of the Cavity Down type for use in HF application. A Faraday Cage is realized to protect the active element from external HF wave interferences. The lateral sides of the Faraday Cage are constituted by a row of solder balls connected in a zig-zag way to plated through holes along the four edges of the substrate. The top side of the Cage is the metal stiffener of the Cavity Down package electrically connected to the through holes, while the bottom side is represented by the ground plane of the main board properly connected to the solder balls.