Patents Examined by Brain E. Hearn
  • Patent number: 5314842
    Abstract: A resin-sealed type semiconductor device comprises a lead frame having a bed and external leads, a semiconductor element mounted on the bed and having electrodes, a fine metal wire for making an electrical connection between the electrode and the lead frame, a resin layer which seals the semiconductor element, fine metal wire and portion of the lead frame therein and a recess formed at a central portion of one surface side of the resin layer and having a controlled depth, whereby the development of cracks in the resin layer as caused by heat load is prevented.
    Type: Grant
    Filed: September 14, 1992
    Date of Patent: May 24, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiromichi Sawaya, Toshio Ishigami
  • Patent number: 5266157
    Abstract: There is provided a method for anisotropic etching of a fine resist pattern at a practically useful etching rate wherein micro-loading effects are suppressed. If a resist layer is etched using an NH.sub.3 /N.sub.2 gas mixture, while the temperature of a sample wafer is controlled to be not higher than 50.degree. C., a reaction product containing at least N, C and O is produced. The micro-loading effects are suppressed because deposition and sputtering of the reaction product occur competitively on the wafer surface. Since etching of the ion mode is accelerated by N.sub.2, the etching rate as well as anisotropy is improved. There ia also provided a method of supplying sulfur to a NH.sub.3 -containing etching reaction system and utilizing the yielded ammonium sulfide for sidewall protection for further improving anisotropy.
    Type: Grant
    Filed: October 3, 1991
    Date of Patent: November 30, 1993
    Assignee: Sony Corporation
    Inventor: Shingo Kadomura
  • Patent number: 5093273
    Abstract: A semiconductor device comprising three recessed portions formed at a very small pitch on the surface of a semiconductor substrate, remaining regions formed between these recessed portions as impurity diffused regions serving as the source and the drain, respectively, and a conductive region as a gate electrode formed through an insulating film within the central recessed portion, and a method of manufacturing such a semiconductor device are disclosed. With this device, its gate length can be made shorter than that in the prior art and the junction leakage is reduced, resulting in miniaturization and an improvement in the characteristics.
    Type: Grant
    Filed: July 3, 1990
    Date of Patent: March 3, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Katsuya Okumura
  • Patent number: 5093283
    Abstract: A surface layer (10), for example oxide, is provided on a first major surface (2) of a semiconductor body (1). A masking layer (11) having at least one window (12) is defined on the surface layer (10). The surface layer (10) and the semiconductor body (1) are etched through the window (12) to define an opening (13in the surface layer (10) and a recess (14) within the semiconductor body (1) extending beneath the surface layer (10) so that a rim portion (10a) of the surface layer (10) overhangs the recess (14). The rim portion (10a) of the surface layer (10) is removed by causing a settable flowable material (15) to flow onto the surface layer (10) and into the recess (14) and then causing the flowable material to set and thereby change volume to apply a force for causing the rim portion (10a) to break away from the remainder ( 10b) of the surface layer (10). The set flowable material (150) and thus the rim portion (10a) of the surface layer (10) are then removed.
    Type: Grant
    Filed: May 16, 1991
    Date of Patent: March 3, 1992
    Assignee: U.S. Philips Corporation
    Inventor: Colin M. Rowe
  • Patent number: 5010019
    Abstract: A semiconductor device operating in a high frequency range is formed in structure capable of facilitating and highly accurate frequency characteristic test. A semiconductor substrate (1) is provided on a major surface with an input electrode pad (2a) and an output electrode pad (2b) to be connected with integrated circuits included in the semiconductor substrate (1) respectively, while grounding electrode pads (2c) are formed each with paired grounding lines disposed on both sides of the input and output electrode pads (2a, 2b), respectively, to sandwich the same. The grounding electrode pads (2c) ground the semiconductor substrate (1) in a high frequency characteristic test.
    Type: Grant
    Filed: April 24, 1990
    Date of Patent: April 23, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takayuki Katoh
  • Patent number: 5008217
    Abstract: Direct contact to shallow junctions in integrated circuits and interconnection between these contacts is achievable by utilizing a specific aluminum CVD process. In this process the aluminum is deposited utilizing a triisobutyl aluminum precursor onto a substrate having a nucleation layer, e.g. a titanium nitride layer. By appropriate choice of this nucleation layer to control the nucleation of the depositing aluminum, suitable contact is made while avoiding void defects present in the absence of such layer.
    Type: Grant
    Filed: June 8, 1990
    Date of Patent: April 16, 1991
    Assignee: AT&T Bell Laboratories
    Inventors: Christopher J. Case, Kin P. Cheung, Ruichen Liu, Ronald J. Schutz, Richard S. Wagner
  • Patent number: 4800139
    Abstract: An excellent stable hydrogen electrode of low polarization is provided which comprises Raney nickel catalyst containing about 0.2-2% by weight of chromium. Such hydrogen electrode is produced safely without spontaneous ignition of the catalyst by mixing and kneading a powder of the catalyst and a suspension liquid of polytetrafluoroethylene (PTFE) while dehydrating at low temperature.
    Type: Grant
    Filed: September 28, 1987
    Date of Patent: January 24, 1989
    Assignee: Muroran Institute of Technology
    Inventor: Tadao Kenjyo
  • Patent number: 4468856
    Abstract: In semiconductor devices, the transistors are isolated by means of either a PN junction isolation method or a passive isolation (PI) method. The present invention aims to improve the PI method, which is disadvantageous in that an electrode, electrically connected to the semiconductor substrate, causes a decrease in the integration density of the IC chip. In the present invention, the vacant space outside the element-forming regions is used to form the electrode and the integration density is not decreased due to the formation of the electrode. Since a polycrystalline silicon layer is in a groove formed in the vacant space, ohmic contact between the polycrystalline semiconductor material in the layer and the semiconductor substrate can be achieved while at the same time keeping the diffusion length of the impurities diffused from the polycrystalline silicon layer and the semiconductor substrate, very short. Therefore, upward diffusion of the impurities from the N.sup.
    Type: Grant
    Filed: March 22, 1982
    Date of Patent: September 4, 1984
    Assignee: Fujitsu Limited
    Inventor: Toshitaka Fukushima
  • Patent number: 4445271
    Abstract: A ceramic chip carrier having a lead frame thereon with a removable lead frame support which does not bond to the ceramic during the bonding procedure and is later removed. A perforated ground pad is bonded to the substrate simultaneously with the leads of the lead frame and is attached to the lead frame support. The support area is of reduced thickness relative to the rest of the lead frame so that it does not come in contact with the ceramic substrate during the bonding procedure. After firing and bonding of the lead frame to the substrate, the unbonded support rim is removed by pinch cutting, etching or the like.
    Type: Grant
    Filed: August 14, 1981
    Date of Patent: May 1, 1984
    Assignee: AMP Incorporated
    Inventor: Dimitry G. Grabbe