Patents Examined by Brain K. Young
  • Patent number: 5818377
    Abstract: A bipolar, element averaging, digital to analog signal converter including a delta-sigma digital to analog converter (".increment..SIGMA. DAC") with dual sequence controllers for controlling the switching sequences of the array of sampling capacitors used to sample a fixed reference voltage in the sample and hold amplifier. The sequence controllers receive the input digital signal and a sign bit which indicates whether the numeric value of the digital signal is positive or negative with respect to the mean value of its total dynamic range. Based upon the sign bit and the value of the digital signal, the sequence controllers generate two sets of switching sequence control signals: "positive" and "negative." Those digital signals whose numeric values are positive and negative with respect to the mean value are considered to be "positive" and "negative" signals, respectively, with corresponding positive and negative analog signals generated accordingly.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: October 6, 1998
    Assignee: National Semiconductor Corporation
    Inventor: James Brian Wieser
  • Patent number: 5535082
    Abstract: A turn-on control circuit having a comparator supplied with a turn-on voltage increasing gradually during the turn-on phase of a device for protection. When the control voltage reaches a predetermined value, the comparator supplies a diagnostic enabling signal to a diagnostic stage, which, in the event an undesired condition is detected at an output of the device, supplies a clamp enabling signal to the control terminal of a clamping transistor located between the input of the circuit and ground, and which, when enabled, prevents the turn-on voltage from increasing further, and so prevents the device from being turned on.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: July 9, 1996
    Inventors: Edoardo Botti, Andrea Fassina
  • Patent number: 5479169
    Abstract: An improved analog-to digital converter employs multiple sample and hold circuits to simultaneously supply multiple neural network A/D converters with samples of an analog input voltage so that the neural networks may simultaneously perform conversion of the different samples into a lower-order portion of the digital signals. A single fast A/D converter converts each sample into a higher-order portion of each digital signal.
    Type: Grant
    Filed: June 7, 1994
    Date of Patent: December 26, 1995
    Assignee: Louisiana Simchip Technologies, Inc.
    Inventor: Wieslaw Stryjewski
  • Patent number: 5465092
    Abstract: An ADC system in which raw ADC data is received and digitally manipulated to increase the accuracy of the resultant digital output word. In one embodiment, the digital manipulation of this invention is performed on data which has been preliminarily adjusted for errors caused by use of an interstage gain less than ideal. In one embodiment, digital correction is performed based only on the errors of a plurality of most significant bit stages, rather than all stages, as the effect on error of the digital output word is of decreasing importance for stages of less significance. In accordance with one embodiment of this invention, offset error and full scale error are determined by applying .+-.Vref as an input signal to the ADC. These values allow the raw digital data from the ADC to be compensated in either hardware or software to provide a more accurate digital representation of the analog input voltage being measured.
    Type: Grant
    Filed: January 19, 1994
    Date of Patent: November 7, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Michael K. Mayes, Sing W. Chin
  • Patent number: 4811018
    Abstract: An analog-to-digital conversion system for converting an analog signal to a digital signal for recording is configured to detect a low level period of the analog signal, amplify a low noise in the analog signal in the detected period by a predetermined multiplying ratio or by an amount corresponding to the signal amplitude, and subtract from the converted digital signal a number of bits corresponding to the amplification degree in the same period after analog-to-digital conversion, so as to reduce the influence of a noise entering in the analog signal before analog-to-digital conversion.
    Type: Grant
    Filed: February 9, 1987
    Date of Patent: March 7, 1989
    Assignee: Clarion Co., Ltd.
    Inventor: Haruo Sakata