Abstract: A power supply voltage reset circuit, provided in an apparatus having an internal circuit capable of adjusting an internal power supply voltage, for resetting the internal circuit when a power supply voltage of the apparatus rises, and includes: a unit that generates an internal power supply voltage reference signal and changes a signal level thereof; a unit that generates an internal reference voltage to be a reference level in generating a reset signal for the internal circuit at a time of rising of the power supply voltage; a unit that generates a power-on adjustment voltage which rises later than the internal reference voltage at the time of rising of the power supply voltage and becomes greater than the internal reference voltage after a predetermined time passes; and a unit that generates the reset signal by comparing the internal reference voltage with the power-on adjustment voltage.

Abstract: A starting apparatus includes: a storage unit storing an identifier; a rectifying unit rectifying a reception signal; a generating unit comparing the reception signal rectified in the rectifying unit to a reference signal and generating a digital signal from the reception signal; a judging unit judging whether or not the digital signal contains information of the identifier; a reference changing unit changing the reference signal when the judging unit judges that the reception signal does not contain information of the identifier; and a start instructing unit instructing start of an electric appliance when the judging unit judges that the reception signal contains information of the identifier.

Abstract: A disclosed embodiment is a data retention flip flop comprising master and slave circuits that are configured to be turned off when a single sleep mode signal is activated. The disclosed embodiment also comprises an always-on balloon circuit coupled to the master circuit, where the always-on balloon circuit includes a common sub-circuit shared with the master circuit. The master circuit writes into the always-on balloon circuit when the single sleep mode signal is activated, and the master circuit reads from the always-on balloon circuit when the single sleep mode signal is deactivated. The always-on balloon circuits comprises high threshold voltage transistors, while the slave circuit comprises low threshold voltage transistors. The master and slave circuits have no leakage current, or substantially no leakage current, after the single sleep mode signal is activated.

Abstract: Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. On or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.

Abstract: In one embodiment of the invention, a method for convolution of signals is disclosed including generating four phased half duty cycle clocks each being out of phase by a multiple of ninety degrees from the others; coupling the four phased half duty cycle clocks into a four phase half duty cycle mixer; and switching switches in the four phase half duty cycle mixer in response to the four phased half duty cycle clocks to convolve a differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port.

Abstract: In one embodiment of the invention, a method is disclosed to generate a clock output signal with selected phase. The method includes selecting a phase delay for the clock output signal; charging a capacitor with a first weighted current during a first phase input clock, charging the capacitor with a second weighted current during a portion of a second phase input clock, and determining if a voltage across the capacitor is greater than or equal to a threshold voltage to generate a first edge of the clock output signal with the selected phase delay. The first weighted current may have a weighting of N out of M to charge the capacitor with a predetermined rate of change in voltage in response to the selected phase delay. The second weighted current may have a weighting of M out of M to charge the capacitor with a constant rate of change.

Abstract: A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.

Abstract: The invention provides a charge pump circuit which reduces rise time of an output current even when an input signal is of high frequency. PMOS1 and PMOS2 have gates connected to each other, and the gate of the PMOS1 is connected to the drain thereof. A supply potential (Vdd) is applied to the sources of the PMOS1 and the PMOS2, and the PMOS1 and the PMOS2 form a current mirror circuit. First and second switching elements and a first constant-current source are connected to the drain of the PMOS2. A connection point (a node) of the first switching element and the second switching element is connected to an output terminal. The drain of the PMOS1 is connected to the first constant-current source through a third switching element, and connected to a second constant-current source through a fourth switching element.

Abstract: An arrangement for transmitting magnetic resonance signals, with a transmission link that connects a local coil with a receiver, has a first channel of the local coil with a first single antenna to acquire a first magnetic resonance signal, as well as a first mixer connected with the first single antenna. The first mixer forms an intermediate-frequency first signal from the supplied first magnetic resonance signal. A second channel of the local coil has a second single antenna to acquire a second magnetic resonance signal, as well as a second mixer connected with the second single antenna. The second mixer forms an intermediate-frequency second signal from the supplied second magnetic resonance signal. The local coil has a device for signal combination that, by frequency multiplexing, that combines the intermediate-frequency first signal of the first channel and the intermediate-frequency second signal of the second channel so that it arrives at the receiver via the transmission path.

Abstract: An arctangent detector according to the present invention generates a demodulated signal based on the result of arctangent calculation of the ratio between an in-phase component and a quadrature component obtained from a frequency modulation (FM) received signal that are perpendicular to each other. A median filter substitutes the median value of the sample values obtained by sampling the demodulated signal generated by the arctangent detector as many times as the point number for the current value of the demodulated signal and outputs a resultant signal. The point number altering unit alters the point number in the median filter based on the signal intensity of the FM received signal.

Abstract: A semiconductor device includes a plurality of synchronization clock generators configured to generate a plurality of synchronization clock signals by mixing phases of first and second source clock signals having an identical frequency, a first clock transmission path configured to sequentially apply the first source clock signal to the plurality of synchronization clock generators by transferring the first source clock signal in a forward direction, a second clock transmission path configured to sequentially apply the second source clock signal to the plurality of synchronization clock generators by transferring the second source clock signal in a backward direction, and a plurality of data output units configured to synchronize a plurality of data with the plurality of synchronization clock signals and outputting the synchronized plurality of data.

Abstract: Circuits, demultiplexers, and methods are disclosed. A circuit includes a reference clock input to receive clock pulses at a reference clock speed. An internal divided clock input receives a divided clock signal from a clock divider that is driven by the clock pulses. The clock divider generates the divided clock signal at a second clock speed that is a fraction of the reference clock speed. An external divided clock input receives an external divided clock signal. The external divided clock signal is driven by the clock pulses and operates at the second clock speed. A clock transition synchronization circuit suppresses application of one or more of the clock pulses to the clock divider when the divided clock signal transitions between clock states out of synchronization with the external divided clock signal.

Abstract: This application discloses a device that has a power-on reset generator. The power-on reset generator can include a power-on detector that receives an input electrical signal and outputs a digital signal that has predetermined value when the voltage of the input electrical signal exceeds a threshold voltage. The power-on detector can include multiple voltage-shaping elements arranged in series. Each voltage-shaping element can have a P-channel transistor and an N-channel transistor that differs in strength with respect to the P-channel transistor. The power-on detector can also include a switch that locks the digital signal at the predetermined value when the voltage of the input electrical signal exceeds the voltage threshold. In addition to the power-on detector, the power-on reset generator can include a digital delay that receives both the digital signal and a clock signal.

Abstract: Multistage charge pumps with diode loss compensation are disclosed. In one example, a pre-regulated charge pump to generate a voltage is described. The example pre-regulated charge pump includes a charge pump having a plurality of stages and one or more diodes. The stages are configured to generate an output voltage at an output terminal based on an input voltage and a number of the multiplier stages. The example pre-regulated charge pump also includes a pre-regulator stage configured to adjust the input voltage to remove dependency on supply voltage variation. The pre-regulator includes a feedback diode configured to compensate for one or more voltage drops associated with the one or more charge pump diodes.

Abstract: A wireless network connection system remotely connects to a network without the use of crystal reference oscillators. This provides communication at long range using a low transmit Effective Isotropic Radiated Power (EIRP). Operation is obtained through a combination of injection locking the system clock to the fundamental frequency of a remote reference oscillator, injection locking the transmitter to the third harmonic of the remote reference oscillator, a micro-watt RF receiver, and a network connection.

Abstract: A clock gater includes a first circuit configured to receive a clock signal. The first circuit includes a first subcircuit and a second subcircuit. A latch is configured to receive the clock signal. The latch is connected to the first circuit at each of a first node and a second node. The latch includes a third subcircuit and a fourth subcircuit. The first subcircuit and the third subcircuit are configured to pull the first node and the second node, respectively, to a common precharge voltage in response to a first state of the clock signal in order to pass the clock signal. The second subcircuit and the fourth subcircuit are configured to pull the first node and the second node, respectively, to complementary voltages in response to a second state of the clock signal in order to pass the clock signal, the second state of the clock signal being different from the first state of the clock signal.