Abstract: A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.

Abstract: Systems and processes for statistics management in a distributed storage system using a flat cluster architecture. Statistics for managed objects are collected using virtual statistics groups across multiple storage nodes. The systems and processes are compatible with storage systems that utilize microservice architectures.

Abstract: A determination is made in a multi-processor system that a cache storage is storing a first type of elements and a second type of elements, wherein on an average each of the first type of elements takes a longer time to destage to secondary storage in comparison to each of the second type of elements. A determination is made of how many tasks to run for scanning the cache storage and destaging the first type of elements and the second type of elements from the cache storage, based on how many of first type of elements and how many of the second type of elements are stored in the cache storage, and how many processors are available in the multi-processor system.

Abstract: Systems and methods for improving data refresh in flash memory are described. In one embodiment, the method includes identifying a first garbage collection unit (GCU) of the storage system, computing a parity function in relation to the first GCU, identifying a data impairment in a first block, the first block being from the N blocks in the first GCU, removing the first block from the first GCU after identifying the data impairment in the first block, and recomputing the parity function when the first block is not cloned.

Abstract: Hardware-based translation lookaside buffer (TLB) invalidation techniques are disclosed. A host system is configured to exchange data with a peripheral component interconnect express PCIE) endpoint (EP). A memory management unit (MMU), which is a hardware element, is included in the host system to provide address translation according to at least one TLB. In one aspect, the MMU is configured to invalidate the at least one TLB in response to receiving at least one TLB invalidation command from the PCIE EP. In another aspect, the PCIE EP is configured to determine that the at least one TLB needs to be invalidated and provide the TLB invalidation command to invalidate the at least one TLB. By implementing hardware-based TLB invalidation in the host system, it is possible to reduce TLB invalidation delay, thus leading to increased data throughput, reduced power consumption, and improved user experience.

Abstract: A memory system includes: a non-volatile memory device including a normal region in which Most Significant Bits (MSBs) and Least Significant Bits (LSBs) stored in memory cells are accessed simultaneously, a hot region in which MSBs stored in memory cells are accessed, and a cold region in which LSBs stored in memory cells are accessed; and a memory controller controlling the non-volatile memory device, Herein, the memory controller includes: a read/write counter that counts the number of read operations and the number of write operations that are performed for each of logical cluster to thereby produce a counting result; and a region selector that maps each logical cluster to one among the normal region, the hot region and the cold region based on the counting result to thereby produce mapping data.