Patents Examined by Brian Dufton
  • Patent number: 6165891
    Abstract: A method and structure for forming a damascene structure with reduced capacitance by forming one or more of: the passivation layer, the etch stop layer, and the cap layer using a low dielectric constant material comprising carbon nitride, boron nitride, or boron carbon nitride. The method begins by providing a semiconductor structure having a first conductive layer thereover. A passivation layer is formed on the first conductive layer. A first dielectric layer is formed over the passivation layer, and an etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over the etch stop layer, and an optional cap layer can be formed over the second dielectric layer. The cap layer, the second dielectric layer, the etch stop layer, and the first dielectric layer are patterned to form a via opening stopping on said passivation layer and a trench opening stopping on the first conductive layer.
    Type: Grant
    Filed: November 22, 1999
    Date of Patent: December 26, 2000
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yi Xu, Mei Sheng Zhou