Patents Examined by Brian E. Heran
  • Patent number: 5434094
    Abstract: FET devices according to the invention are made by etching separation grooves and the via-holes from the front surface of the substrate. Thereafter, the thickness of the substrate is reduced from the rear surface to expose the plating in the via-holes and separation grooves. A rear surface electrode and a plated heat sink are sequentially deposited on the rear surface of the thinned substrate. The devices are divided from a wafer by etching and/or severing along the separation grooves and at opposed locations along the plated heat sink.
    Type: Grant
    Filed: April 8, 1994
    Date of Patent: July 18, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Michihiro Kobiki, Masahiro Yoshida, Takahide Ishikawa