Abstract: The gate voltage breakdown of an integrated circuit field effect transistor, expecially a compound semiconductor metal semiconductor field effect transistor (MESFET) and high electron mobility transistor (HEMT) is dramatically increased by forming an electron trap layer on the surface of the device, under the gate contact and extending beyond the gate contact towards the drain contact. The electron trap layer is preferably a high resistivity lattice matched monocrystalline layer having at least 10.sup.18 traps per cubic centimeter. For gallium arsenide based transistors, the electron trap layer is preferably formed by low temperature molecular beam epitaxy (MBE) of gallium and arsenic fluxes, to produce a monocrystalline gallium arsenide layer having 1% excess arsenic. For indium phosphide based transistors, the electron trap layer is preferably formed by low temperature MBE of aluminum, indium and arsenic fluxes to produce a monocrystalline aluminum indium arsenide layer having 1% excess arsenic.

Abstract: A structure and method for forming a semicustom integrated circuit in which customization can be performed using only a single masking step. Vias in an insulation layer between first and second metal are made larger than first metal lines so that after deposition of second metal, a final patterning etch can remove not only portions of the second metal to leave interconnect lines but can also remove second metal within any exposed vias and additionally remove first metal in order to disconnect selected portions of first metal lines. In order for the final etch step not to remove portions of the substrate, an extra step of planarizing the insulation layer between first and second metal is provided. The large vias provided by the structure and method also allow for shrinking the size of first and second metal lines and thus shrinking the metal line width required by the design rules for the entire semiconductor structure.

Abstract: A vertical semiconductor device having a plurality of vertical active regions and a method for manufacturing such a vertical semiconductor device. In the preferred embodiment, a vertical multicollector pnp transistor is formed by disposing a plurality of n type epitaxial layers over a bottom p type substrate. Each epitaxial layer has a plurality of collector regions formed therein. The collector regions are connected using a single diffusion step to form vertical collectors for the pnp transistor. The base is formed from the epitaxial layers and the emitter is formed using a separate implant or diffusion step. Vertical isolation regions are formed contemporaneously with the vertical collectors. The resulting pnp transistor has vertical collectors and isolation regions formed with less silicon, fewer diffusion steps, and more precise and reduced dimensions.