Abstract: A microelectronics device including a semiconductor device located at least partially over a substrate, a bombarded area located at least partially over the substrate and adjacent the semiconductor device, and a bombarded attenuator interposing the semiconductor device and the bombarded area.

Abstract: A resin material having low dielectric constant is used as an inter-layer insulating film and its bottom surface is contacted with a silicon oxide film across the whole surface thereof. Thereby, the surface may be flattened and capacity produced between a thin film transistor and an pixel electrode may be reduced. Further, it allows to avoid a problem that impurity ions and moisture infiltrate into the lower surface of the resin material, thus degrading the reliability of whole semiconductor device.

Abstract: A nitride based 3-5 group compound semiconductor light emitting device comprising: a substrate; a buffer layer formed above the substrate; a first In-doped GaN layer formed above the buffer layer; an InxGa1—xN/InyGa1?yN super lattice structure layer formed above the first In-doped GaN layer; a first electrode contact layer formed above the InxGa1—xN/InyGa1?yN super lattice structure layer; an active layer formed above the first electrode contact layer and functioning to emit light; a second In-doped GaN layer; a GaN layer formed above the second In-doped GaN layer; and a second electrode contact layer formed above the GaN layer. The present invention can reduce crystal defects of the nitride based 3-5 group compound semiconductor light emitting device and improve the crystallinity of a GaN GaN based single crystal layer in order to improve the performance of the light emitting device and ensure the reliability thereof.

Abstract: Integrated circuit devices are provided including an integrated circuit substrate and first through fourth spaced apart lower interconnects on the integrated circuit substrate. The third and fourth spaced apart lower interconnects are parallel to the first and second lower interconnects. A first fuse is provided on the first and second lower interconnects between the first and second lower interconnects and is electrically coupled to the first and second lower interconnects. A second fuse is provided spaced apart from the first fuse and on the third and fourth lower interconnects. The second fuse is between the third and fourth lower interconnects and is electrically coupled to the third and fourth lower interconnects. Related methods of fabricating integrated circuit devices are also provided.

Abstract: A diode circuit includes a pin diode structure, wherein the n-semiconductor layer is a buried layer, on which the i-area is deposited by an epitaxy method, and wherein a p-semiconductor layer is introduced into the epitaxy layer. A contacting of the p-semiconductor layer and a contacting of the n-semiconductor layer are arranged on the same main surface of the semiconductor substrate so that an integration with an integrated capacitor, an integrated resistor and/or an integrated inductor is possible.

Abstract: The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a quantum island 120 situated between the source and drain, to form tunnel junctions 125, 130 between the source and drain. The device further includes a fixed-gate electrode 135 located adjacent the quantum island 120. The fixed-gate electrode has a capacitance associated therewith that varies as a function of an applied voltage to the fixed-gate electrode. The present invention also includes a method of fabricating a single-electron device 300, and a transistor circuit 800 that include a single-electron device 810.

Abstract: The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor device. The resistor includes first and second crystalline layers which may or may not differ from one another. One of the first and second crystalline layers comprises doped silicon/germanium, and the other comprises doped silicon. The transistor device and resistor can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). The invention also includes processes of forming semiconductor constructions, and in particular aspects, includes processes of forming resistor constructions.

Abstract: A non-volatile semiconductor memory device with a small variation in capacitance-coupling to the stacked gate for memory miniaturization. The device has a memory cell array in which memory cells are arranged in array. Each cell has a first gate and a second gate on a semiconductor substrate. The first gate is formed, via a first gate insulating film, on each of device forming regions isolated by device-isolating insulating films. The second gate is formed on the first gate via a second gate insulating film. The first gate is patterned so that its portion is overlapped on the isolation insulating film from the device forming region. A protective insulating film is provided on the isolation film between the device forming regions and in the vicinity of the first gate. A charge-storage layer of each memory cell has at least two stacked conductive layers with a small isolation width at a low aspect ratio for burying isolation insulating films for high density, to easily fabricate in low cost.

Abstract: A method is provided to enhance the connection reliability in three-dimensional mounting while considering the warping of packages. Opening diameters of the openings provided corresponding to protruding electrodes, respectively, are set so as to gradually decrease from the central portion toward the outer peripheral portion of a carrier substrate, and the opening diameters of openings provided corresponding to the protruding electrodes, respectively, are set so as to gradually decrease from the central portion toward the outer peripheral portion of another carrier substrate.

Abstract: A light-emitting apparatus employing a GaN-based semiconductor. The light-emitting apparatus comprises an n-type clad layer (124); an active layer (129) including an n-type first barrier layer (126), well layers (128), and second barrier layers (130); a p-type block layer (132); and a p-type clad layer (134). By setting the band gap energy Egb of the p-type block layer (132), the band gap energy Eg2 of the second barrier layers (130), the band gap energy Eg1 of the first barrier layer (126), and the band gap energy Egc of the n-type and the p-type clad layers such that the relationship Egb>Eg2>Eg1?Egc is satisfied; the carriers can be efficiently confined; and the intensity of the light emission can be increased.

Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.

Abstract: The present invention provides a dual organic field-effect transistor (OFET) structure and a method of fabricating the structure. The dual OFET structure includes an n-type organic semiconductor layer and a p-type organic semiconductor layer in contact with each other along an interface and forming a stack. The dual OFET structure also includes a source electrode and a drain electrode, the source and drain electrodes being in contact with one of the organic semiconductor layers. The dual OFET structure further includes first and second gate structures located on opposite sides of the stack. The first gate structure is configured to control a channel region of the n-type organic semiconductor layer, and the second gate structure is configured to control a channel region of the p-type organic semiconductor layer.