Patents Examined by Brian H. Hearn
  • Patent number: 5420050
    Abstract: The present invention teaches a method and structure of enhancing the current gain characteristics of a bipolar junction transistor. The method comprises the step of forming a patterned silicon dioxide layer superjacent a semiconductor substrate comprising a base, an emitter and a collector, such that a carrier current conducts between the base and the emitter. The silicon dioxide layer forms an interface on the substrate at the emitter. Further, a first polysilicon layer is formed superjacent both the patterned silicon dioxide layer and the interface, and is implanted with O.sub.2. Subsequently, the substrate is heated such that the emitter interface is obstructed by a silicon dioxide formation, thereby blocking a portion of carrier current from passing through the interface.
    Type: Grant
    Filed: December 20, 1993
    Date of Patent: May 30, 1995
    Assignee: United Technologies Corporation
    Inventors: Rick C. Jerome, Ian R. C. Post, Gary M. Wodek