Abstract: A memory controller capable of estimating memory power consumption includes a memory control unit, a command dispatch device, plural bank state machines and a power-state and current-accumulation device. The memory control unit generates control signals based on a memory access command sent by a system for accessing a synchronous dynamic random access memory (SDRAM). The command dispatch device synchronously receives the control signals sent by the controller to the SDRAM. The plural bank state machines are connected to the command dispatch device to receive the control signals dispatched by the command dispatch device and accordingly determine whether to transfer its internal state or not. The power-state and current-accumulation device determines on which state the SDRAM is in accordance with states of the plural band state machines, thereby computing current consumption of the SDRAM.

Abstract: A device for DRAM initialization of a computer system. A detection circuit detects memory condition and outputs a fast initialization signal. A buffer stores initialization parameters of the memory. A memory controller sets the initialization parameters according to memory information, and reads the memory condition to initialize the memory when booting and receiving the fast initialization signal.