Patents Examined by Brian Johnson
  • Patent number: 7370180
    Abstract: A method of controlling data processing logic which causes a data value to be rotated by a number of bits in order to generate a rotated data value; a number of least significant bits of the rotated data value are masked with other bits of said rotated data value not being masked in order to generate a masked rotated data value; a selected bit of said rotated data value are masked with other bits of said rotated data value not being masked in order to generate a bit preset rotated data value; and said sign-extended bit field extracted data value to be generated by subtracting said masked rotated data value from said bit preset data value or said zero-extended bit field extracted data value to be generated by performing a logical exclusive-OR operation with the masked rotated data value and said bit preset data value.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: May 6, 2008
    Assignee: ARM Limited
    Inventors: Alexander Edward Nancekievill, David James Seal
  • Patent number: 7269717
    Abstract: One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the STE instruction. Changes made during this transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: September 11, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Marc Tremblay, Shailender Chaudhry, Quinn A. Jacobson
  • Patent number: 7246219
    Abstract: Methods and apparatus are disclosed to control power consumption within a processor. An example processor disclosed herein comprises an instruction retirement unit; a first set of functional blocks to process a first set of instructions having a first instruction type; a second set of functional blocks to process a second set of instructions having a second instruction type; and a controller to enable the first set of functional blocks to process an instruction allocated to the instruction retirement unit if the type of the instruction is the first type, and to disable the first set of functional blocks after the instruction is retired by the instruction retirement unit.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: July 17, 2007
    Assignee: Intel Corporation
    Inventors: Nicholas G. Samra, Andrew S. Huang, Namratha R. Jaisimha
  • Patent number: 7222227
    Abstract: A device and method for implementing prediction verification control and recovery control in speculative instruction execution when a prediction error occurs with simple hardware configuration are disclosed. This device includes a branch instruction insertion unit that dynamically inserts a branch instruction subsequent to a target instruction for prediction in a group of instructions consisting of the target instruction for prediction for which a value is to be predicted and a subsequent instruction. An instruction issuing unit speculatively issues a subsequent instruction to an execution unit without waiting for the execution result of the target instruction for prediction and an execution unit executes the issued instructions.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: May 22, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Katayama, Masashi Sasahara
  • Patent number: 7216216
    Abstract: In one embodiment, a processor is configured to execute a window swap instruction. The processor comprises a register file (that comprises a plurality of registers) and first and second execution units coupled to the register file. A first pipeline associated with the first execution unit has a first number of pipeline stages, and a second pipeline associated with the second execution unit has a second number of pipeline stages. The first execution unit is configured to change the current register window from the first register window to the second register window in the register file in response to the instruction. The second execution unit is configured to perform an operation defined by the instruction and write the result to the register file. The second number of pipeline stages exceeds the first number, whereby the second register window is established in the register file prior to writing the result.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: May 8, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Christopher H. Olson, Jeffrey S. Brooks, Robert T. Golla
  • Patent number: 7178008
    Abstract: A parallel processor has a plurality of operation units that execute operation instructions, and a multi-bank register file in which a plurality of banks each having a plurality of registers are formed. Each of machine instructions, which are input simultaneously, is split into a plurality of nano-instructions each of which includes at least one of an access instruction and operation instruction. The output clock cycles of operation instructions with respect to the operation units are arbitrated. Furthermore, the output clock cycles of access instructions to the multi-bank register file are arbitrated so as to prevent access instructions from contending in an identical bank in the multi-bank register file.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: February 13, 2007
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Tetsuo Hironaka, Mattausch Hans Juergen, Takeshi Hiramatsu
  • Patent number: 7178010
    Abstract: An internal call/return stack (CRS) correction apparatus in a pipelined microprocessor is disclosed. Each time the microprocessor updates the CRS in response to a call or return instruction (call/ret), the microprocessor also stores correction information into a first correction stack. The microprocessor includes two distinct stages that detect invalidating events, such as a branch misprediction or exception. Once a call/ret passes the first detecting stage, the correction information associated with that call/ret is moved from the first correction stack to a second correction stack. If an invalidating event is detected at the upper detecting stage, then only the correction information in the first stack is used to correct the CRS. However, if an invalidating event is detected at the lower detecting stage, then the correction information in both the first and second stack is used to correct the CRS.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: February 13, 2007
    Assignee: IP-First, LLC
    Inventor: Thomas C. McDonald
  • Patent number: 7162617
    Abstract: A program counter having an independent context for each virtual processor is provided, and a non-native instruction fetched from a main memory based on address information generated by the program counter is classified by property by an instruction classifying unit. Then an instruction merge information memory is read out utilizing address information prescribed for each classified group as reference address, and native execution control information is merged and executed. Selection and switching of the virtual processor is performed through selectively switching the instruction classifying unit and an active portion of the instruction merge information memory, and the switching timing is appropriately adjusted by synchronizing with a switching enabling signal output from the instruction merge information memory.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: January 9, 2007
    Assignee: Fine Arc Incorporated
    Inventors: Ken Ota, Toshiyuki Kochi
  • Patent number: 7134000
    Abstract: An instruction alignment unit for aligning instructions in a digital processor having a pipelined architecture includes an instruction queue, a current instruction buffer and a next instruction buffer in a pipeline stage n, an aligned instruction buffer in a pipeline stage n+1, instruction fetch logic for loading instructions into the current instruction buffer from an instruction cache or from the next instruction buffer and for loading instructions into the next instruction buffer from the instruction cache or from the instruction queue, and alignment control logic responsive to instruction length information contained in the instructions for controlling transfer of instructions from the current instruction buffer and the next instruction buffer to the aligned instruction buffer.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: November 7, 2006
    Assignee: Analog Devices, Inc.
    Inventors: Thang M. Tran, Ravi Pratap Singh, Deepa Duraiswamy, Srikanth Kannan
  • Patent number: 7124284
    Abstract: A method and apparatus to determine readiness of a complex instruction for retirement includes decoding a complex instruction into a plurality of helper instructions; executing the plurality of helper instructions using an execution unit; indicating the plurality of helper instructions that are alive using a live instruction register; and maintaining a complex instruction identification for the complex instruction using a complex instruction identification register.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: October 17, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Rabin A. Sugumar, Sorin Iacobovici, Chandra M. R. Thimmannagari
  • Patent number: 7103755
    Abstract: An apparatus for efficient parallel executing instruction avoiding the usage of cross bypasses, the apparatus including an instruction buffer for storing instructions, of decoders for decoding, in parallel, the instructions which simultaneously issue from the instruction buffer, executing units for executing the instructions decoded in the decoders, and an instruction-issuing controlling means for controlling the issuing of the instructions in such a way that, when the instructions are executed, one of the plural executing units executes instructions more frequently than the rest of the plural executing units. The apparatus is preferably incorporated in an information processor to superscalar or out-of-order instruction execution.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: September 5, 2006
    Assignee: Fujitsu Limited
    Inventors: Susumu Akiu, Masaki Ukai, Toshio Yoshida
  • Patent number: 7103754
    Abstract: A computer architecture that provides the definition of a 20 bit signed displacement value used to form the operand storage address.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: September 5, 2006
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Check, Brian B. Moore, Timothy J. Slegel
  • Patent number: 6761366
    Abstract: A portable tool container comprises a molded tub and removable cover with wheels attached to one side of the container on opposite sides of a telescoping handle in a housing that is integrally molded into the container.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: July 13, 2004
    Assignee: Waterloo Industries
    Inventors: Ramon L. Klemmensen, Michael E. Hay, Fred P. Ritchie, Steven F. Kohagen
  • Patent number: 6729629
    Abstract: A detachable roller skate comprises a boot comprising a front cavity, a rear cavity, and an elongate plate interconnected the cavities wherein each cavity has two resilient side protrusions and a rear projection; and a truck comprising a sole plate, an engagement plate threadedly secured to sole plate, a front abutment member on top of engagement plate having a neck and a rear projected member above neck, a rear opening in engagement plate, a front upright projection in rear opening, an internal spring receptacle, a channel extended from rear opening to a rear end of engagement plate, and a push block comprising a front flat, a rear elongated plate, a stop member above flat, two side grooves at stop member, an abutted member on top of stop member, and two side dents at abutted member being perpendicular to and in communication with side grooves. The invention can easily fasten boot and truck or unfasten the same.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: May 4, 2004
    Assignee: Wever Co., Ltd.
    Inventor: Owen Chi
  • Patent number: 6715784
    Abstract: A method of operating a wheelchair during an un-recline process involves a wheelchair having tilt and recline functions, the wheelchair including a seat frame, a tilt actuator for tilting the seat frame, a back frame, a recline actuator for reclining the back frame. A sensor for determining the angle of recline is provided. A controller for controlling the tilt actuator and recline actuator is also provided. The controller is provided with a plurality of preprogrammed sequences for moving the seat frame and the back frame during an unrecline procedure. The sequences include tilting the seat frame as an initial part of the unrecline sequence, wherein the sequences are a function of the initial angle of recline at the initiation of the recline sequence. An initial angle of recline at the initiation of a recline sequence is determined, and the back frame is unreclined according to one of the preprogrammed sequences in response to the determined initial angle of recline.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: April 6, 2004
    Assignee: Sunrise Medical HHG Inc.
    Inventors: James M. Koerlin, Mark E. Greig
  • Patent number: 6672415
    Abstract: In a hybrid vehicle with fuel cells and an engine mounted thereon as energy output sources, a technique is employed that adequately changes a working energy output source according to a driving state of the hybrid vehicle. The hybrid vehicle has the engine and a motor, both enabling power to be output to an axle. The hybrid vehicle also has fuel cells as a main electric power supply for driving the motor. The technique changes the working energy output source between the fuel cells and the engine, in order to reduce the output of the fuel cells with consumption of a fuel for the fuel cells. With a decrease in remaining quantity of the fuel, the technique narrows a specific driving range, in which the motor is used as the power source. The technique also causes the engine to drive the motor as a generator and charges a battery not with electric power of the fuel cells but with electric power generated by the motor.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: January 6, 2004
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Atsushi Tabata
  • Patent number: 6467777
    Abstract: An in-line skate with power assistance has at least two rollers attached to a base, the at least two rollers aligned to form an in-line axis such that the at least two rollers travel along a surface in essentially a single travel line and a power roller aligned outward of the at least two rollers. A bias mechanism coupled between the power roller and the base, the bias mechanism is responsive to pressure on the power roller when contacting the surface to adjust position of the power roller relative to the base. The power roller is adjustable and resiliently mounted to be positioned above the skating surface when gliding. The power roller makes with contact the skating surface when pushing, the pressure on the power roller being varied by the bias mechanism.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: October 22, 2002
    Inventor: J. Gary Teyhen
  • Patent number: 6416063
    Abstract: Inline roller skates are provided with independent suspension systems, separately suspending one or more of a plurality of wheels. The wheels are mounted rotatably on axles, and the axles are held nominally parallel to the sole of the boot. The suspension systems include guides that maintain the axles parallel to the sole of the boot even as the wheels and axles move vertically in response to bumps and other forces.
    Type: Grant
    Filed: July 13, 1999
    Date of Patent: July 9, 2002
    Inventors: Scott H. Stillinger, Daniel M. Humes
  • Patent number: 6390492
    Abstract: A soft boot snowboard binding system having tool-less adjustments to permit a custom fit for maximum comfort and control. The adjustments, once made, are secure against unwanted release caused by environmental elements or hard use. A quick-release lever and buckle provide fast in and out action upon easy manual operation of the buckle, but resists all unwanted releases or jamming from snow build-up. A tool-less forward lean adjuster carries a concealed philips screwdriver bit which inserts into the adjuster plate to provide a screwdriver to tighten mounting screws or other fasteners on the snowboard binding, as needed.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: May 21, 2002
    Assignee: Sidway Sports, LLC
    Inventors: Scott E. Bumgarner, Ryan P. Bumgarner
  • Patent number: 6247711
    Abstract: A sulky that comprises an upper support having a seat attached thereto via a seat support member and further having at each end an outer frame member and an inner frame member; a pair of axles, each of which are disposed between one of the outer and the inner frame members, and onto which are rotatably mounted, via a wheel hub, a pair of wheels; a pair of shafts for harnessing the sulky to a horse, each of the shafts having a pivot connection along its length; and a pair of fork assemblies, each having a pair of forks which are joined at one end so as to be pivotably secured to the pivot connection along one of the shafts. The unjoined ends of the forks are rotatably connected to one of the axles on opposite sides of the wheel hub. The wheels are configured to pivot around said pivot connection upon the exertion of a sideways displacement force at the wheels. In one embodiment of the invention, each of the pair of axles is horizontally slidably secured to the outer and inner frame members.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: June 19, 2001
    Inventor: Michael Saraydar