Abstract: N-channel devices are fabricated with lightly doped drain/source extensions in a CMOS process, without the requirement of an extra mask level. A merged mask technique uses an oversized version of the N-channel gates, expanded by two alignment tolerances per side, combined with the regular N+ source/drain mask. The oversized gate photoresist prevents the heavy N+ source/drain implant from counterdoping the previously introduced lightly doped drain blanket implant. In the P-channel regions the N-type LDD extensions are counterdoped by the regular P+ source/drain implant. This high-voltage process provides 20 V parts with 4 micron geometries, scalable to other voltages.

Abstract: A field effect transistor has improved punch-through resistance by the implantation of a dose of ions through the center of the active area. The energy of the dose is such that the ion concentration peaks at the depth most susceptible to punch-through. The threshold voltage of the transistor is set by the combination of a lower than normal threshold implant and the tail concentration of the blocking implant.