Abstract: A method and apparatus for accessing and manipulating a stack register file during an instruction execution through a pipelined execution unit. A plurality of control directives are provided to the apparatus. A stack register file having a plurality of physical registers is provided for storing data. The physical register file has a stack organization. A pointer table register file having a plurality of pointer table registers stores physical register addresses. A TAG register file comprising a plurality of TAG registers, one for each of the pointer table register, is provided for signalling whether the associated physical register is empty or full. A TOS address generator generates an address of one of the pointer table registers which contains an address of one of the physical registers which is the current top of stack register.

Abstract: A data processing apparatus which operates on instruction controlling plural processor actions. Each instruction includes a data unit section and an independent data transfer section. The data unit section includes a data operation field that indicates the type of arithmetic logic unit operation and six operand fields. The six operand fields include four source data register fields and two destination register fields. The data unit (110) includes a multiplication unit (220) and an arithmetic logic unit (230). The data unit (110) may include a barrel rotator (235) for one input of the arithmetic logic unit (230). The rotated data may be stored in the first destination register instead of the multiply result. The address unit (120) operations according to the data transfer operation field. This could be a load, a store or a register to register move. Operations may be conditional based upon conditions stored in a status register (210) set by a prior output of the arithmetic logic unit (230).

Abstract: A multi-port buffer stores digitized image and/or audio information from a video camera and transfers the stored image information to a plurality of output channels. Digitized input data is passed through a crossbar switch and stored in a random access memory (RAM). The image data is retrieved from RAM and passed the crossbar switch to one of a plurality of first-in, first-out (FIFO) registers. Raster scan lines are passed from the FIFO registers to corresponding output channels. The order and rate of writing to RAM and reading out to the FIFO registers is controlled by an asynchronous queuing arbiter. If one of the output channels is slower than the others or operates at a variable clock speed, the asynchronous queuing arbiter changes the order in which the FIFO registers are filled to accommodate that output channel. Should one of the output channels fail, the bus request for the corresponding FIFO register is disabled, thereby skipping the failed channel.

Abstract: A radial clock distribution system that converts a standard bus clock signal into two pairs of inverted and non-inverted clocking signals. The two pairs of clocking signals have a lower frequency, have a different phase, and are shifted one clock period apart. The clocking signals are transferred over a first set of signal lines of equal length and impedance to computing systems components that are connected to a synchronous bus. Each component includes at least one clock repeater chip to convert the clocking signals (e.g., change these signals to a 5 volt CMOS level) to a different format. The converted clocking signals are then transferred over a second set of signal lines of equal length and impedance to the gate arrays. The gate arrays includes direct drive circuitry that receives the converted clocking signals and transmits these signals to internal driver circuitry. These signals are transferred over low skew lines.

Abstract: In a superscalar processor capable of executing two integer instructions in parallel, an array of comparators is provided to check for all combinations of register dependency between a pair of sequential program instructions. Additional logic is provided to validate the register fields of the instructions. If no impermissible dependencies are detected and all register fields are valid, the instructions are issued and executed in parallel. Otherwise, the instructions are executed sequentially.

Abstract: An apparatus and method for accessing a plurality of computer devices having common memory or input-output addresses on buses operating at different speeds. The present invention detects a CPU address request and issues a local bus acknowledge thereto which prevents the CPU core logic from processing the instruction on the other buses. The present invention processes the instruction and upon completion thereof, asserts both CPU BOFF and READY signals on the computer system local bus. The CPU receives the BOFF signal, releases control of the local bus and ignores the READY signal. When the present invention releases the asserted BOFF signal, it then ignores the next local bus cycle because this next local bus signal will be the same as the previous bus cycle. The next CPU bus cycle contains the same information as the previous cycle, and the computer system core logic issues appropriate commands to the other bus interface such as an ISA bus.

Abstract: In a fault simulator for simulating a logic circuit model which is operable in response to first through n-th input pattern signals, a signal generating circuit implemented by hardware generates the first through the n-th input pattern signals. The logic circuit model is assorted into first through m-th levels and is defined by first through p-th faults. The fault simulator carries out a plurality of simulations at the same time in each of the first through the m-th levels. When the simulation proceeds to the m-th level, the fault simulator produces a simulation result signal representative of detected faults and a correct value. The fault simulator simulates the first through the p-th faults by the use of each of the first through the n-th input pattern signals.

Abstract: A large burst mode memory accessing system includes N discrete sub-memories and three main I/O ports. Data is stored in the sub-memories so that the sub-memories are accessed depending on their proximity to the main I/O ports. Three parallel pipelines provide a data path to/from the main I/O ports and the sub-memories. The first pipeline functions to couple address/control signals to the memories such that adjacent sub-memories are accessed in half cycle intervals. The second pipeline functions to propagate accessed data from the sub-memories to the main I/O ports such that data is outputted from the main output port every successive clock cycle. The third pipeline propagates write data to the memories such that data presented at the input of the third pipeline on successive clock cycles is written into successive sub-memories. Redundancy circuits preserve data integrity without memory access interruption.

Abstract: Improved techniques for predicting a branch target address using a branch history table (BHT), is disclosed. The BHT stores a plurality of pairs of a branch address and corresponding branch target address. In order to eliminate or effectively reduce loss of machine cycles in the branch target address prediction, a prefetched address data is compared with an incoming new branch instruction address before being applied to a BHT (branch history table) for the purpose of updating same. When the coincidence is detected, a selector selects a new branch target address before being applied to the BHT. The selected new branch target address is fed to an instruction address prefetch register.

Abstract: A data processor wherein, in the case where an instruction decoder has decoded a multi-data transfer (storing or loading) instruction, bits in a register list outputted from the instruction decoder are searched by first and second priority encoders to encode respectively a position of "1" (or "0") and a position where "1" (or "0") is continued in two bits as binary digits, and when the encoded results do not coincide only one register corresponding to a bit position of the single "1" (or "0") is accessed, when the encoded results coincide the registers corresponding to the bit positions of the two continuous "1" (or "0") are accessed at the same time to process the multi-data transfer instruction effectively.

Abstract: A logic simulation system and method reduces the number of events to be simulated. The simulator receives a user specified circuit netlist denoting a specified logic circuit's components and the nodes interconnecting those components. A user specified watched nodes list identifies the circuit nodes for which output waveforms are to be generated. A cell library provides cell delay data representing signal delays from each input port to each output port of each circuit component. A set of input signal waveforms are compiled into a sequence of variable length time periods and each input signal is assigned an extended boolean value for each time period. The extended boolean values identify signals that are stable over the time period, signals with a single transition during the time period, and signals with multiple transitions during the time period.

Abstract: In an information processing system operable in response to a branch condition signal which is representative of branch conditions and which is divisible into first and second groups produced a first and second output groups, a preliminary branch selection circuit selects either one of the first and the second output groups in response to a predetermined signal as a selected output group. A specific one of the branch conditions is selected from the selected output group by a first selection switch in response to a branch condition selecting signal produced from a microinstruction read out of a control memory. A specific branch condition is used to carry out a branch operation. The predetermined signal may be produced by an internal hardware of the information system, a specific microinstruction, specific program instructions, or a combination of a specific program instruction and a specific microinstruction.